Page 1 Cyclone V Hard Processor System Technical Reference Manual Last updated for Quartus Prime Design Suite: 16.1 cv_5v4 101 Innovation Drive Subscribe 2016.10.28 San Jose, CA 95134 Send Feedback www.altera.com...
Page 2: Table Of Contents
Clock Manager Module Address Map..................2-24 Document Revision History........................2-73 Reset Manager..................... 3-1 Reset Manager Block Diagram and System Integration................. 3-2 HPS External Reset Sources......................3-3 Reset Controller..........................3-4 Module Reset Signals........................3-5 Slave Interface and Status Register....................3-10 Functional Description of the Reset Manager..................3-10 Altera Corporation...
Page 3 System Manager Address Map and Register Definitions................5-9 System Manager Module Address Map..................5-9 Document Revision History........................5-237 Scan Manager.......................6-1 Features of the Scan Manager........................6-1 Scan Manager Block Diagram and System Integration................6-2 ARM JTAG-AP Signal Use in the Scan Manager.................6-2 Altera Corporation...
Page 4 The Global Programmers View...................... 8-4 Functional Description of the FPGA-to-HPS Bridge..............8-4 Functional Description of the HPS-to-FPGA Bridge............... 8-19 Functional Description of the Lightweight HPS-to-FPGA Bridge..........8-32 Clocks and Resets...........................8-51 Data Width Sizing.......................... 8-53 HPS-FPGA Bridges Address Map and Register Definitions..............8-53 Altera Corporation...
Page 5 Document Revision History........................9-73 CoreSight Debug and Trace................10-1 Features of CoreSight Debug and Trace....................10-2 ARM CoreSight Documentation......................10-2 CoreSight Debug and Trace Block Diagram and System Integration..........10-3 Functional Description of CoreSight Debug and Trace................10-4 Debug Access Port......................... 10-4 System Trace Macrocell.........................10-4 Altera Corporation...
Page 6 MPFE SDRAM Burst Scheduling....................11-13 Single-Port Controller Operation....................11-14 SDRAM Power Management......................... 11-24 DDR PHY..............................11-25 DDR Calibration.......................... 11-25 Clocks................................ 11-25 Resets................................. 11-26 Taking the SDRAM Controller Subsystem Out of Reset ............11-26 Port Mappings............................11-26 Initialization..............................11-27 FPGA-to-SDRAM Protocol Details...................11-28 Altera Corporation...
Page 7 Local Memory Buffer........................13-6 Clocks.............................. 13-6 Resets............................... 13-7 Indexed Addressing........................13-7 Command Mapping........................13-8 Data DMA.............................13-14 ECC..............................13-18 NAND Flash Controller Programming Model..................13-21 Basic Flash Programming......................13-22 Flash-Related Special Function Operations................13-25 NAND Flash Controller Address Map and Register Definitions............13-33 Altera Corporation...
Page 8 Interface Signals............................15-3 Functional Description of the Quad SPI Flash Controller..............15-3 Overview............................15-3 Data Slave Interface........................15-4 SPI Legacy Mode..........................15-7 Register Slave Interface........................15-8 Local Memory Buffer........................15-8 DMA Peripheral Request Controller...................15-9 Arbitration between Direct/Indirect Access Controller and STIG........15-10 Altera Corporation...
Page 9 Instructions...........................16-35 Assembler Directives........................16-50 MFIFO Buffer Usage Overview....................16-52 DMA Controller Address Map and Register Definitions..............16-60 Address Map and Register Definitions..................16-62 Document Revision History........................16-63 Ethernet Media Access Controller..............17-1 Features of the Ethernet MAC........................17-2 MAC..............................17-2 DMA..............................17-2 Altera Corporation...
Page 10 USB OTG Controller Block Diagram and System Integration............18-4 USB 2.0 ULPI PHY Signal Description....................18-5 Functional Description of the USB OTG Controller................18-6 USB OTG Controller Block Description..................18-6 Local Memory Buffer........................18-10 Clocks............................18-10 Resets............................. 18-10 Interrupts............................18-11 USB OTG Controller Programming Model..................18-13 Altera Corporation...
Page 11 C Controller Block Diagram and System Integration................20-2 C Controller Signal Description......................20-3 Functional Description of the I C Controller..................20-4 Feature Usage..........................20-4 Behavior............................20-5 Protocol Details..........................20-6 Multiple Master Arbitration....................... 20-11 Clock Frequency Configuration....................20-13 SDA Hold Time..........................20-15 Altera Corporation...
Page 12 Functional Description of the GPIO Interface..................22-3 Debounce Operation........................22-3 Pin Directions..........................22-3 Taking the GPIO Interface Out of Reset ..................22-3 GPIO Interface Programming Model..................... 22-4 General-Purpose I/O Interface Address Map and Register Definitions..........22-4 GPIO Module Address Map......................22-4 Document Revision History........................22-22 Altera Corporation...
Page 13 L4 Watchdog Module Address Map.................... 24-7 Document Revision History........................24-21 CAN Controller....................25-1 Features of the CAN Controller....................... 25-1 CAN Controller Block Diagram and System Integration..............25-2 Functional Description of the CAN Controller..................25-3 Message Object..........................25-3 Message Interface Registers......................25-7 Altera Corporation...
Page 14 PLL Reference Clocks........................27-10 Peripheral FPGA Clocks......................27-11 Configuring Peripheral Pin Multiplexing..................... 27-11 Configuring Peripherals......................27-12 Connecting Unassigned Pins to GPIO..................27-12 Using Unassigned IO as LoanIO....................27-13 Resolving Pin Multiplexing Conflicts..................27-13 Peripheral Signals Routed to FPGA ..................27-13 Configuring the External Memory Interface..................27-14 Altera Corporation...
Page 15 Generating the HPS Simulation Model in Qsys................ 29-5 Running the Simulations.......................29-5 Clock and Reset Interfaces........................29-9 Clock Interface..........................29-9 Reset Interface..........................29-10 FPGA-to-HPS AXI Slave Interface......................29-11 HPS-to-FPGA AXI Master Interface.....................29-11 Lightweight HPS-to-FPGA AXI Master Interface................29-12 FPGA-to-HPS SDRAM Interface......................29-13 Altera Corporation...
Page 16 L4 Watchdog 0 Timer........................A-26 Preloader............................A-26 U-Boot Loader..........................A-26 Boot ROM Flow............................A-26 Typical Preloader Boot Flow........................A-28 HPS State on Entry to the Preloader...................A-31 Shared Memory..........................A-31 Loading the Preloader Image.......................A-32 FPGA Configuration..........................A-33 Full Configuration.........................A-33 Partial Reconfiguration.........................A-34 Document Revision History........................A-35 Altera Corporation...
Page 17: Introduction To The Hard Processor System
• Debug components • Phase-locked loops (PLLs) 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos © are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants...
Page 18 You can also turn off the FPGA portion of the device while leaving the HPS power on. Table 1-1: Valid SoC Power Modes FPGA Valid? Related Information • Booting and Configuration on page 30-1 • Cyclone V Device Datasheet Introduction to the Hard Processor System Altera Corporation Send Feedback...
Page 19: Features Of The Hps
• System manager • Clock manager • Reset manager • Scan manager • FPGA manager • SDRAM controller subsystem Two of the four I Cs, provide support for general purpose. Introduction to the Hard Processor System Altera Corporation Send Feedback...
Page 20: Hps Block Diagram And System Integration
Cache L3 Master 32-Bit Peripheral EMAC 32-Bit Switch 32-Bit 32-Bit Boot ROM SDRAM Controller Subsystem 32-Bit 64-Bit On-Chip RAM SDRAM Controller Altera PHY 32-Bit Single-Port Interface Memory 32-Bit NAND Controller 32-Bit Flash 64-Bit 32-Bit HPS I/O Pins 32-Bit Quad L3 Slave Peripheral Switch...
Page 21: Cortex-A9 Mpcore
HPS Block Diagram on page 1-4 HPS Interfaces The Cyclone V device family provides multiple communication channels to the HPS. HPS–FPGA Memory-Mapped Interfaces The HPS–FPGA memory-mapped interfaces provide the major communication channels between the HPS and the FPGA fabric. The HPS–FPGA memory-mapped interfaces include: •...
Page 22: System Interconnect
• FPGA fabric interface with up to six ports that can be combined for a data width up to 256-bits wide using Avalon-MM and AXI interfaces. The SDRAM controller subsystem is composed of the SDRAM controller, DDR PHY, control and status registers and their associated interfaces. Introduction to the Hard Processor System Altera Corporation Send Feedback...
Page 23: On-Chip Memory
The boot ROM offers the following features: • 64 KB size • Contains the code required to support HPS boot from cold or warm reset • Used exclusively for booting the HPS Introduction to the Hard Processor System Altera Corporation Send Feedback...
Page 24: Flash Memory Controllers
• Programmable delays between transactions • Programmable device sizes • Support eXecute-In-Place (XIP) mode • Programmable baud rate generator to generate device clocks Related Information Quad SPI Flash Controller on page 15-1 Introduction to the Hard Processor System Altera Corporation Send Feedback...
Page 25: Support Peripherals
Clock Manager on page 2-1 Does not support SDR50, SDR104, and DDR50 modes. Does not support SDR50, SDR104, and DDR50 modes. Does not support DDR mode. Does not support DDR mode. Introduction to the Hard Processor System Altera Corporation Send Feedback...
Page 26 • 32-bit timer resolution • Interrupt request • Reset request • Programmable time-out period up to approximately 86 seconds (assuming a 50 MHz input clock frequency) Related Information Watchdog Timer on page 24-1 Introduction to the Hard Processor System Altera Corporation Send Feedback...
Page 27: Interface Peripherals
• Gigabit media independent interface (GMII) • Reduced gigabit media independent interface (RGMII) • Serial gigabit media independent interface (SGMII) supported through the GMII to FPGA fabric with additional external conversion logic Introduction to the Hard Processor System Altera Corporation Send Feedback...
Page 28 127 devices, each having 32 endpoints (IN + OUT), for a maximum of 4,064 endpoints. • Supports generic root hub • Supports automatic ping capability Introduction to the Hard Processor System Altera Corporation Send Feedback...
Page 29 • Supports 11-bit standard and 29-bit extended identifiers • Programmable interrupt scheme • Direct access for host processor • DMA controller may be used for large transfers Related Information CAN Controller on page 25-1 Introduction to the Hard Processor System Altera Corporation Send Feedback...
Page 30: Coresight Debug And Trace
• Supports up to 67 dedicated I/O pins and an additional 14 input-only pins Related Information General-Purpose I/O Interface on page 22-1 CoreSight Debug and Trace The CoreSight debug and trace system offers the following features: Introduction to the Hard Processor System Altera Corporation Send Feedback...
Page 31: Endian Support
(BE8). All other masters, including the USB 2.0 interface, are little endian. Registers in the MPU and L2 cache are little endian regardless of the endian mode of the CPUs. Note: Altera strongly recommends that you only use little endian. The FPGA–to–HPS, HPS–to–FPGA, FPGA–to–SDRAM, and lightweight HPS–to–FPGA interfaces are little endian.
Page 32 The following table shows the base address and size of each region that is common to the L3 and MPU address spaces. Table 1-2: Common Address Space Regions Region Name Base Address Size FPGA slaves 0xC0000000 960 MB Peripheral 0xFC000000 64 MB Lightweight FPGA slaves 0xFF200000 2 MB Introduction to the Hard Processor System Altera Corporation Send Feedback...
Page 33: Hps Peripheral Region Address Map
Table 1-3: Peripheral Region Address Map Slave Identifier Description Base Address Size Space Trace Macrocell 0xFC000000 48 MB Debug Access Port 0xFF000000 2 MB Introduction to the Hard Processor System Altera Corporation Send Feedback...
Page 34 1 MB USB0 USB 2.0 OTG 0 controller 0xFFB00000 256 KB registers USB1 USB 2.0 OTG 1 controller 0xFFB40000 256 KB registers NANDREGS NAND flash controller 0xFFB80000 64 KB registers Introduction to the Hard Processor System Altera Corporation Send Feedback...
Page 35 16 KB DMANONSECURE DMA nonsecure registers 0xFFE00000 4 KB DMASECURE DMA secure registers 0xFFE01000 4 KB SPIS0 SPI slave 0 0xFFE02000 4 KB SPIS1 SPI slave 1 0xFFE03000 4 KB Introduction to the Hard Processor System Altera Corporation Send Feedback...
Page 36: Document Revision History
MPU L2 cache controller 0xFFFEF000 4 KB registers OCRAM On-chip RAM 0xFFFF0000 64 KB Related Information Cyclone V Address Map and Register Definitions Web-based address map and register definitions Document Revision History Table 1-4: Document Revision History Date Version Changes October 2016 2016.10.28 •...
Page 37 1-21 Document Revision History 2016.10.28 Date Version Changes May 2012 Added peripheral region address map. January 2012 Initial release. Introduction to the Hard Processor System Altera Corporation Send Feedback...
Page 38: Clock Manager
• Safe mode for Hardware-Managed clocks • General-purpose I/O (GPIO) debounce clock divide 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos © are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants...
Page 39: Clock Manager Block Diagram And System Integration
• on page 2-7 Clock Manager Block Diagram and System Integration Figure 2-1: Clock Manager Block Diagram The following figure shows the major components of the clock manager and its integration in the HPS. Clock Manager Altera Corporation Send Feedback...
Page 40: L4 Peripheral Clocks
Note: Select it as a test clock. Always used as the PHY domain clock utmi_clk during DFT Scan mode. Note: Select as a test clock utmi_clk even when the core is configured for a non-UTMI PHY. Clock Manager Altera Corporation Send Feedback...
Page 41: Functional Description Of The Clock Manager
Clock manager provides CSR bits for software enables to some peripherals. These enables are defaulted to enable. In boot mode, these enables are automatically active to ensure all clocks are active if RAM is cleared for security. Clock Manager Altera Corporation Send Feedback...
Page 42 • Phase shift of 1/8 per step • Phase shift range is 0 to 7 Related Information Cyclone V Device Datasheet FREF, FVCO, and FOUT Equations Figure 2-2: PLL Block Diagram Values listed for M, N, and C are actually one greater than the values stored in the CSRs.
Page 43 For the full bit field of the vco register, refer to the Address Map and Register Definitions section. Dividers Dividers subdivide the C0-C15 clocks produced by the PLL to lower frequencies. The main PLL C0-C2 clocks have an additional internal post-scale counter. Clock Manager Altera Corporation Send Feedback...
Page 44: Hardware-Managed And Software-Managed Clocks
HPS reset and clock input pins power supply ( HPS_CLK1 HPS_CLK2 _HPS CCRSTCLK For more information on refer to the Cyclone V Device Datasheet. _HPS CCRSTCLK Related Information Cyclone V Device Datasheet OSC1 Clock Group The clock in the OSC1 clock group is derived directly from the pin.
Page 45 Orange-colored clock gating logic is controlled by hardware. Orange-colored clock gating logic allows hardware to seamlessly transition a synchronous set of clocks, for example, all the MPU subsystem clocks. The maximum frequency depends on the speed grade of the device. Clock Manager Altera Corporation Send Feedback...
Page 46 Table 2-6: Main Clock Group Clocks System Clock Name Frequency Constraints and Notes Main PLL C0 Clock for MPU subsystem, mpu_clk including CPU0 and CPU1 Clock for MPU level 2 (L2) RAM mpu_clk mpu_l2_ram_clk Clock Manager Altera Corporation Send Feedback...
Page 47 Input clock to flash controller main_nand_sdmmc_clk clocks block to 100_MHz divided from FPGA manager configuration osc1_clk cfg_clk main PLL C5 clock to 100_MHz divided from Auxiliary user clock to the FPGA osc1_clk h2f_user0_clock main PLL C5 fabric Clock Manager Altera Corporation Send Feedback...
Page 48 Transitions to a different divide value occur on the fastest output clock, one clock cycle prior to the slowest clock’s rising edge. For example, the clock transitions on cycle 15 of the divide-by-16 divider for the main C2 output and cycle 3 of the divide-by-4 divider for the C1 output. Clock Manager Altera Corporation Send Feedback...
Page 49 Clock gate blocks in the diagram indicate clocks that may be gated off under software control. Software is expected to gate these clocks off prior to changing any PLL or divider settings that might create incorrect behavior on these clocks. Clock Manager Altera Corporation Send Feedback...
Page 50 200 MHz for the scan manager Up to 250 MHz Peripheral PLL C0 EMAC0 clock. The emac0_clk 250 MHz clock is divided internally by the EMAC into the typical 125/25/2.5 MHz speeds for 1000/100/ 10 Mbps operation. Clock Manager Altera Corporation Send Feedback...
Page 51 FPGA fabric. Figure 2-5: Flash Peripheral Clock Divide and Gating f2h_periph_ref_clk Clock Gate sdmmc_clk main_nand_sdmmc_base_clk periph_nand_sdmmc_base_clk nand_x_clk f2h_periph_ref_clk Divide by 4 Clock Gate nand_clk Clock Gate main_nand_sdmmc_base_clk periph_nand_sdmmc_base_clk f2h_periph_ref_clk Clock Gate qspi_clk main_qspi_base_clk periph_qspi_base_clk Clock Manager Altera Corporation Send Feedback...
Page 52 SDRAM clock group, an alternate clock source must be selected prior to reconfiguring the FPGA. The counter outputs from the SDRAM PLL can be gated off directly under software control. The divider values for each clock are set by registers in the clock manager. Clock Manager Altera Corporation Send Feedback...
Page 53 Table 2-11: SDRAM Clock Group Clocks Name Frequency Constraints and Notes SDRAM PLL C0 Clock for MPFE, single-port ddr_dqs_clk controller, CSR access, and PHY The maximum frequency depends on the speed grade of the device. Clock Manager Altera Corporation Send Feedback...
Page 54: Resets
. While in safe mode, clock manager register settings, osc1_clk which control clock behavior, are not changed. However, the hardware bypasses these settings and uses safe, default settings. Clock Manager Altera Corporation Send Feedback...
Page 55: Interrupts
Note: Before coming out of safe mode, all registers and clocks must be configured correctly. It is possible to program the clock manager in such a way that only a cold reset can return the clocks to a functioning state. Altera strongly recommends using Altera-provided libraries to configure and control HPS clocks.
Page 56 ACP ID mapper slave and L2 mpu_l2_ram_clk master connections L4 OSC1 bus master osc1_clk L4 SPIM bus master spi_m_clk L4 SP bus master l4_sp_clk Quad SPI bus slave l4_mp_clk Boot ROM Boot ROM l3_main_clk On-chip RAM On-chip RAM l3_main_clk Clock Manager Altera Corporation Send Feedback...
Page 57 Control slave l4_mp_clk Quad SPI flash controller Reference for serialization qspi_clk Master and slave l4_mp_clk SD/MMC controller SD/MMC internal logic sdmmc_clk Master l4_mp_clk EMAC 0 internal logic EMAC 0 emac0_clk IEEE 1588 timestamp osc1_clk Clock Manager Altera Corporation Send Feedback...
Page 58 SP timer 1 SP timer 1 l4_sp_clk C controller 0 l4_sp_clk C controller 1 l4_sp_clk C controller 2 l4_sp_clk C controller 3 l4_sp_clk UART controller 0 UART 0 l4_sp_clk UART controller 1 UART 1 l4_sp_clk Clock Manager Altera Corporation Send Feedback...
Page 59 CSRs, and PHY SDRAM subsystem Off-chip strobe data ddr_2x_dqs_clk Slave connected to MPU mpu_l2_ram_clk subsystem L2 cache Slave connected to L3 intercon‐ l3_main_clk nect L4 watchdog timer 0 L4 watchdog timer 0 osc1_clk Clock Manager Altera Corporation Send Feedback...
Page 60: Clock Manager Address Map And Register Definitions
• Clock Manager Module Related Information • Introduction to the Hard Processor System on page 1-1 The base addresses of all modules are also listed in the Introduction to the Hard Processor System chapter. http://www.altera.com/literature/hb/cyclone-v/hps.html • Clock Manager Altera Corporation Send Feedback...
Page 61: Clock Manager Module Address Map
2-41 Enable Register on page 2-41 0x60 0x3FF Main Divide Register maindiv on page 2-42 0x64 Debug Divide Register dbgdiv on page 2-44 0x68 Debug Trace Divide Register tracediv on page 2- 0x6C Clock Manager Altera Corporation Send Feedback...
Page 62 2-57 0xA4 GPIO Divide Register gpiodiv on page 2-60 0xA8 Flash Clock Source Register on page 2-61 0xAC 0x15 Peripheral PLL Output Counter stat on page 2-62 0xB0 Reset Ack Status Register Clock Manager Altera Corporation Send Feedback...
Page 63 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved ensfm Reser safemode RW 0x1 Clock Manager Altera Corporation Send Feedback...
Page 64 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved perpl perpl sdrpl sdrpl mainpll lsrc lsrc RW 0x1 Clock Manager Altera Corporation Send Feedback...
Page 65 PLL are directly driven from the Main PLL input clock. The bypass source for Main PLL is the external eosc1_clk. The reset value for this bit is applied on a cold reset. Warm reset has no effect on this bit. Clock Manager Altera Corporation Send Feedback...
Page 66 If 1, the Peripheral PLL has lost lock at least once perplllost since this bit was cleared. If 0, the Peripheral PLL has not lost lock since this bit was cleared. Clock Manager Altera Corporation Send Feedback...
Page 67 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved sdrpl perpl mainp sdrpl perpl mainplla llost llost lllos lachi lachi chieved eved eved RW 0x0 Clock Manager Altera Corporation Send Feedback...
Page 68 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Clock Manager Altera Corporation Send Feedback...
Page 69 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Clock Manager Altera Corporation Send Feedback...
Page 70 Contains settings that control clock mpu_clk generated from the C0 output of the Main PLL. Only reset by a cold reset. mainclk on page 2-38 Contains settings that control clock main_clk generated from the C1 output of the Main PLL. Only reset by a cold reset. Clock Manager Altera Corporation Send Feedback...
Page 71 (M+1) and divided by the denominator (N+1). The VCO input clock source is always eosc1_clk. Fields are only reset by a cold reset. Module Instance Base Address Register Address clkmgr 0xFFD04000 0xFFD04040 Offset: 0x40 Access: Clock Manager Altera Corporation Send Feedback...
Page 72 If set to '1', reset output divider, no clock output from counter. If set to '0', counter is not reset. The reset value of this bit is applied on a cold reset; warm reset has no effect on this bit. Clock Manager Altera Corporation Send Feedback...
Page 73 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Clock Manager Altera Corporation Send Feedback...
Page 74 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Clock Manager Altera Corporation Send Feedback...
Page 75 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 mainclk Fields Name Description Access Reset Divides the VCO/4 frequency by the value+1 in this field. Clock Manager Altera Corporation Send Feedback...
Page 76 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Clock Manager Altera Corporation Send Feedback...
Page 77 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x3 mainnandsdmmcclk Fields Name Description Access Reset Divides the VCO frequency by the value+1 in this field. Clock Manager Altera Corporation Send Feedback...
Page 78 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Clock Manager Altera Corporation Send Feedback...
Page 79 Contains fields that control clock dividers for main clocks derived from the Main PLL Fields are only reset by a cold reset. Module Instance Base Address Register Address clkmgr 0xFFD04000 0xFFD04064 Offset: 0x64 Access: Clock Manager Altera Corporation Send Feedback...
Page 80 The l4_mp_clk is divided down from the periph_ l4mpclk base_clk by the value specified in this field. Value Description Divide By 1 Divide By 2 Divide By 4 Divide By 8 Divide By 16 Reserved Reserved Reserved Clock Manager Altera Corporation Send Feedback...
Page 81 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved dbgclk dbgatclk RW 0x1 RW 0x0 Clock Manager Altera Corporation Send Feedback...
Page 82 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved traceclk RW 0x0 Clock Manager Altera Corporation Send Feedback...
Page 83 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved l4sp l4mp RW 0x0 Clock Manager Altera Corporation Send Feedback...
Page 84 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved outresetack RO 0x0 Clock Manager Altera Corporation Send Feedback...
Page 85 Contains settings that control clock periph_qspi_clk generated from the C2 output of the Peripheral PLL. Only reset by a cold reset. pernandsdmmcclk on page 2-54 Contains settings that control clock periph_nand_sdmmc_clk generated from the C3 output of the Peripheral PLL. Only reset by a cold reset. Clock Manager Altera Corporation Send Feedback...
Page 86 Module Instance Base Address Register Address clkmgr 0xFFD04000 0xFFD04080 Offset: 0x80 Access: Bit Fields regextse outreset outre psrc denom setal RW 0x0 RW 0x0 RW 0x1 RW 0x1 numer pwrdn bgpwrdn RW 0x1 RW 0x1 Clock Manager Altera Corporation Send Feedback...
Page 87 23:22 Controls the VCO input clock source. Qsys and user psrc documenation refer to f2s_periph_ref_clk as f2h_ periph_ref_clk. Value Description eosc1_clk eosc2_clk f2s_periph_ref_clk Clock Manager Altera Corporation Send Feedback...
Page 88 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved saten faste bwadj bwadjen RW 0x1 RW 0x0 Clock Manager Altera Corporation Send Feedback...
Page 89 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x1 emac0clk Fields Name Description Access Reset Divides the VCO frequency by the value+1 in this field. Clock Manager Altera Corporation Send Feedback...
Page 90 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Clock Manager Altera Corporation Send Feedback...
Page 91 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x1 pernandsdmmcclk Fields Name Description Access Reset Divides the VCO frequency by the value+1 in this field. Clock Manager Altera Corporation Send Feedback...
Page 92 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Clock Manager Altera Corporation Send Feedback...
Page 93 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved qspic nandc nandx sdmmc s2fus gpioc can1c can0c spimc usbcl emac1 emac0clk er1cl RW 0x1 Clock Manager Altera Corporation Send Feedback...
Page 94 Enables clock emac0_clk output emac0clk Contains fields that control clock dividers for clocks derived from the Peripheral PLL Fields are only reset by a cold reset. Module Instance Base Address Register Address clkmgr 0xFFD04000 0xFFD040A4 Offset: 0xA4 Clock Manager Altera Corporation Send Feedback...
Page 95 The can1_clk is divided down from the periph_base_ can1clk clk by the value specified in this field. Value Description Divide By 1 Divide By 2 Divide By 4 Divide By 8 Divide By 16 Reserved Reserved Reserved Clock Manager Altera Corporation Send Feedback...
Page 96 The spi_m_clk is divided down from the periph_ spimclk base_clk by the value specified in this field. Value Description Divide By 1 Divide By 2 Divide By 4 Divide By 8 Divide By 16 Reserved Reserved Reserved Clock Manager Altera Corporation Send Feedback...
Page 97 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved gpiodbclk RW 0x1 gpiodbclk RW 0x1 Clock Manager Altera Corporation Send Feedback...
Page 98 RW 0x1 RW 0x1 RW 0x1 src Fields Name Description Access Reset Selects the source clock for the QSPI. Qsys and user qspi documenation refer to f2s_periph_ref_clk as f2h_ periph_ref_clk. Value Description f2s_periph_ref_clk main_qspi_clk periph_qspi_clk Clock Manager Altera Corporation Send Feedback...
Page 99 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved outresetack RO 0x0 Clock Manager Altera Corporation Send Feedback...
Page 100 2-70 Contains settings that control clock s2f_user2_clk generated from the C5 output of the SDRAM PLL. Qsys and user documenation refer to s2f_user2_clk as h2f_user2_clk Fields are only reset by a cold reset. Clock Manager Altera Corporation Send Feedback...
Page 101 'Enable' bit is clear, the 'External Regulator Input Select' should be set, and vice versa. The reset value of this bit is applied on a cold reset; warm reset has no effect on this bit. Clock Manager Altera Corporation Send Feedback...
Page 102 20% of the frequency change, this value can be changed without resetting the PLL. The Numerator and Denominator can not be changed at the same time for incremental frequency changed. Clock Manager Altera Corporation Send Feedback...
Page 103 Bit Fields Reserved Reserved saten faste bwadj bwadjen RW 0x1 RW 0x0 ctrl Fields Name Description Access Reset Enables saturation behavior. saten Enables fast locking circuit. fasten 12:1 Provides Loop Bandwidth Adjust value. bwadj Clock Manager Altera Corporation Send Feedback...
Page 104 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved phase RW 0x0 phase RW 0x0 RW 0x1 Clock Manager Altera Corporation Send Feedback...
Page 105 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved phase RW 0x0 phase RW 0x0 RW 0x1 Clock Manager Altera Corporation Send Feedback...
Page 106 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved phase RW 0x0 phase RW 0x0 RW 0x1 Clock Manager Altera Corporation Send Feedback...
Page 107 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved phase RW 0x0 phase RW 0x0 RW 0x1 Clock Manager Altera Corporation Send Feedback...
Page 108 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved s2fus ddrdq ddr2x ddrdqscl er2cl dqscl RW 0x1 Clock Manager Altera Corporation Send Feedback...
Page 109 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved outresetack RO 0x0 Clock Manager Altera Corporation Send Feedback...
Page 110: Document Revision History
2014.06.30 June 2014 E0SC1 changed to HPS_CLK1 E0SC2 changed to HPS_CLK2 Added Address Map and Register Descriptions 2014.02.28 February 2014 Updated content in the "Peripheral Clock Group" section 2013.12.30 December 2013 Minor formatting updates. Clock Manager Altera Corporation Send Feedback...
Page 111 2-74 Document Revision History 2016.10.28 Date Version Changes November 2012 Minor updates. May 2012 • Reorganized and expanded functional description section. • Added address map and register definitions section. January 2012 Initial release. Clock Manager Altera Corporation Send Feedback...
Page 112: Reset Manager
All HPS logic except what is in the TAP and debug reset domains. Includes non- debug logic in the FPGA fabric connected to the HPS reset signals. 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos ©...
Page 113: Reset Manager Block Diagram And System Integration
Reset Manager Block Diagram and System Integration The following figure shows a block diagram of the reset manager in the SoC device. For clarity, reset- related handshaking signals to other HPS modules and to the clock manager module are omitted. Reset Manager Altera Corporation Send Feedback...
Page 114: Hps External Reset Sources
The following table lists the reset sources external to the HPS. All signals are synchronous to the osc1_clk clock. The reset signals from the HPS to the FPGA fabric must be synchronized to your user logic clock domain. Reset Manager Altera Corporation Send Feedback...
Page 115: Reset Controller
_HPS CCRSTCLK Related Information Cyclone V Device Datasheet For information about the required duration of reset request signal assertion, refer to the Cyclone V Device Datasheet. Reset Controller The reset controller performs the following functions: • Accepts reset requests from the FPGA CB, FPGA fabric, modules in the HPS, and reset pins •...
Page 116: Module Reset Signals
In the following tables, columns marked for Cold Reset, Warm Reset, and Debug Reset denote reset signals asserted by each type of reset. For example, writing a 1 to the bit in the register swwarmrstreq ctrl resets all the modules that have a checkmark in the Warm Reset column. Reset Manager Altera Corporation Send Feedback...
Page 117 System usb_rst_n[1:0] Resets NAND flash System nand_flash_rst_n controller Resets quad SPI flash System qspi_flash_rst_n controller Resets each system watchdog System watchdog_rst_n[1:0] timer Resets each OSC1 timer System osc1_timer_rst_n[1:0] Resets each SP timer System sp_timer_rst_n[1:0] Reset Manager Altera Corporation Send Feedback...
Page 118 Debu Software Domai Reset Reset Deassert Reset Resets HPS-to-FPGA Syste hps2fpga_bridge_rst_n AMBA Advanced ® eXtensible Interface (AXI ) bridge ™ Resets FPGA-to-HPS AXI Syste fpga2hps_bridge_rst_n bridge Resets lightweight HPS-to- Syste lwhps2fpga_bridge_rst_n FPGA AXI bridge Reset Manager Altera Corporation Send Feedback...
Page 119 Resets scan manager Syste scan_manager_rst_n Resets freeze controller Syste frz_ctrl_cold_rst_n (resets logic associated with cold reset only) Resets debug masters and Syste sys_dbg_rst_n slaves connected to L3 interconnect and level 4 (L4) buses Reset Manager Altera Corporation Send Feedback...
Page 120 Module Reset Signal Reset Group mpumodrst mpu_cpu_rst_n[1] Ethernet MAC permodrst emac_rst_n[1:0] USB 2.0 OTG permodrst usb_rst_n[1:0] NAND permodrst nand_flash_rst_n Quad SPI permodrst qspi_flash_rst_n Watchdog permodrst watchdog_rst_n[1:0] Timer permodrst osc1_timer_rst_n[1:0] Timer permodrst sp_timer_rst_n[1:0] permodrst i2c_rst_n[3:0] Reset Manager Altera Corporation Send Feedback...
Page 121: Slave Interface And Status Register
Multiple reset requests can be driven to the reset manager at the same time. Cold reset requests take priority over warm and debug reset requests. Higher priority reset requests preempt lower priority reset requests. There is no priority difference among reset requests within the same domain. Reset Manager Altera Corporation Send Feedback...
Page 122: Reset Sequencing
Related Information Cyclone V Device Datasheet For information about the required duration of reset request signal assertion, refer to the Cyclone V Device Datasheet. Reset Sequencing The reset controller sequences resets without software assistance. Module reset signals are asserted asynchronously and synchronously.
Page 123 (1) Cold reset can be initiated from several other sources: FPGA CB, FPGA fabric, modules in the HPS, and reset pins. (2) This dependency applies to all the reset signals. Reset Manager Altera Corporation Send Feedback...
Page 124 2. Wait for 32 cycles. Deassert clock manager cold reset. 3. Wait for 96 cycles (so clocks can stabilize). 4. Proceed to the “Cold and Warm Reset Deassertion Sequence” section using the following link. Reset Manager Altera Corporation Send Feedback...
Page 125 4. Wait for 32 cycles. Deassert resets for MPU modules. 5. Wait for 32 cycles. Deassert for CPU0 and CPU1. mpu_clkoff 6. Peripherals remain held in reset until software brings them out of reset. Reset Manager Altera Corporation Send Feedback...
Page 126: Reset Pins
HPS. You can control the impact of a warm reset on the clocks and I/O elements. Altera strongly recommends using Altera-provided libraries to configure and control this functionality. The default warm reset behavior takes all clocks and I/O elements through a cold reset response. As your software becomes more stable or for debug purposes, you can alter the system response to a warm reset.
Page 127: Reset Handshaking
• Disable safe mode on warm reset—allows software to transition through a warm reset without affecting the clocks. Because the boot ROM code indirectly configures the clock settings after warm reset, Altera recommends that safe mode should only be disabled when the HPS is not booting from a flash device.
Page 128: Reset Manager Module Address Map
STAT register. During the boot process, the Boot ROM copies the STAT register value into memory before clearing it. After booting, you can read the value of the reset status register at memory address ( + 0x0038). Module Instance Base Address Register Address rstmgr 0xFFD05000 0xFFD05000 Reset Manager Altera Corporation Send Feedback...
Page 129 A 1 indicates that Reset Manager's request to the fpgamgrhstimeout FPGA manager to stop driving configuration clock to FPGA CB before starting a hardware sequenced warm reset timed-out and the Reset Manager had to proceed with the warm reset anyway. Reset Manager Altera Corporation Send Feedback...
Page 130 The CTRL register is used by software to control reset behavior.It includes fields for software to initiate the cold and warm reset, enable hardware handshake with other modules before warm reset, and perform Reset Manager Altera Corporation Send Feedback...
Page 131 ETR AXI master start making AXI requests to write trace data. This is the acknowlege for a ETR AXI master stall etrstallack initiated by the ETRSTALLREQ field. A 1 indicates that the ETR has stalled its AXI master Reset Manager Altera Corporation Send Feedback...
Page 132 SCANMGRHSACK to be 1 and then writes this field to 0. Note that it is possible for the Scan Manager to never assert SCANMGRHSACK (e.g. its input clock is disabled) so software should timeout in this case. Reset Manager Altera Corporation Send Feedback...
Page 133 Software waits for the SDRSELFREFACK to be 1 and then writes this field to 0. Note that it is possible for the SDRAM Controller Subsystem to never assert SDRSELFREFACK so software should timeout if SDRSELFREFACK is never asserted. Reset Manager Altera Corporation Send Feedback...
Page 134 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved nrstcnt RW 0x800 nrstcnt warmrstcycles RW 0x800 RW 0x80 Reset Manager Altera Corporation Send Feedback...
Page 135 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved scupe cpu1 cpu0 RW 0x0 Reset Manager Altera Corporation Send Feedback...
Page 136 1. This holds the corresponding module in reset until software is ready to release the module from reset by writing 0 to its field. Module Instance Base Address Register Address rstmgr 0xFFD05000 0xFFD05014 Reset Manager Altera Corporation Send Feedback...
Page 137 Resets CAN0 controller. Writes to this field on devices can0 not containing CAN controllers will be ignored. Resets SD/MMC controller sdmmc Resets SPIS1 controller spis1 Resets SPIS0 controller spis0 Resets SPIM1 controller spim1 Resets SPIM0 controller spim0 Reset Manager Altera Corporation Send Feedback...
Page 138 0 to de-assert the module reset signal. All fields are reset by a cold or warm reset. The reset value of all fields is 1. This holds the corresponding module in reset until software is ready to release the module from reset by writing 0 to its field. Reset Manager Altera Corporation Send Feedback...
Page 139 FPGA Fabric and HPS DMA Controller Resets DMA channel 1 interface adapter between dmaif1 FPGA Fabric and HPS DMA Controller Resets DMA channel 0 interface adapter between dmaif0 FPGA Fabric and HPS DMA Controller Reset Manager Altera Corporation Send Feedback...
Page 140 Software explicitly asserts and de-asserts module reset signals by writing bits in the appropriate *MODRST register. It is up to software to ensure module reset signals are asserted for the appropriate length of time Reset Manager Altera Corporation Send Feedback...
Page 141 (i.e. nTRST pin). Cold reset only. Resets logic located only in the debug domain. Resets logic that spans the system and debug sysdbg domains. Resets Freeze Controller in System Manager (cold frzctrlcold reset only) Resets Scan Manager scanmgr Reset Manager Altera Corporation Send Feedback...
Page 142 The TSTSCRATCH register is used by software as a scratch register to write and read without effecting the reset manager function. Module Instance Base Address Register Address rstmgr 0xFFD05000 0xFFD05054 Offset: 0x54 Access: Bit Fields field0 RW 0x0 field0 RW 0x0 Reset Manager Altera Corporation Send Feedback...
Page 143: Document Revision History
2013.12.30 December 2013 Minor formatting issues. November 2012 • Added cold and warm reset timing diagrams. May 2012 Added reset controller, functional description, and address map and register definitions sections. January 2012 Initial release. Reset Manager Altera Corporation Send Feedback...
Page 144: Fpga Manager
• Generates interrupts based on the FPGA status changes • Can reset the FPGA 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos © are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants...
Page 145: Fpga Manager Block Diagram And System Integration
(CB) when configuring the FPGA portion of the SoC device. The general-purpose I/O and boot handshake input interfaces connect to the FPGA fabric. The FPGA manager also connects to the FPGA CB signals to monitor and control the FPGA portion of the device. FPGA Manager Altera Corporation Send Feedback...
Page 146: Functional Description Of The Fpga Manager
FPGA memory as the next stage in the boot process. There is no interrupt support for this block. Related Information FPGA Manager Address Map and Register Definitions on page 4-9 FPGA Manager Altera Corporation Send Feedback...
Page 147: Fpga Configuration
) pins to determine which configuration scheme to use. MSEL pins must be tied to the appropriate values for the configuration scheme. The table below lists MSEL supported values when the FPGA is configured by the HPS. MSEL FPGA Manager Altera Corporation Send Feedback...
Page 148 Other MSEL values are allowed when the FPGA is configured from a non-HPS source. For information, refer (10) to the Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices. (11) You can select to enable or disable this feature.
Page 149 Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices For more information about configuring the FPGA through the HPS, refer to the "Configuration, Design Security, and Remote System Upgrade in Cyclone V Devices" appendix in the Cyclone V Device Handbook Volume 1: Device Interfaces and Integration.
Page 150 Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices • For more information about configuring the FPGA through the HPS, refer to the "Configuration, Design Security, and Remote System Upgrade in Cyclone V Devices" appendix in the Cyclone V Device Handbook Volume 1: Device Interfaces and Integration. •...
Page 151: Fpga Status
FPGA is not configured the hardware will drive this signal low and it is up to you to drive it high when the memory in the FPGA is ready to accept memory mapped transactions. FPGA Manager Altera Corporation Send Feedback...
Page 152: General Purpose I/O
FPGA Manager Module Configuration Data Address Map Registers in the FPGA Manager module accessible via its AXI slave Base Address: 0xFFB90000 FPGA Manager Module Configuration Data Register Offset Width Acces Reset Value Description Write Data Register data on page 4-10 FPGA Manager Altera Corporation Send Feedback...
Page 153: Fpga Manager Module Address Map
If software reads this register, it returns the value 0 and replies with an AXI SLVERR error. FPGA Manager Module Address Map Registers in the FPGA Manager module accessible via its APB slave Base Address: 0xFF706000 FPGA Manager Altera Corporation Send Feedback...
Page 154 4-41 External Port A Register gpio_ext_porta 0x850 page 4-44 Synchronization Level Register gpio_ls_sync on page 0x860 4-45 GPIO Version Register gpio_ver_id_code 0x86C 0x3230382A page 4-46 Configuration Register 2 gpio_config_reg2 0x870 0x39CEB page 4-47 FPGA Manager Altera Corporation Send Feedback...
Page 155 MSEL inputs from the device pins. The MSEL pins define the FPGA configuration mode. Value Description 16-bit Passive Parallel with Fast Power on Reset Delay; No AES Encryption; No Data Compres‐ sion. CDRATIO must be programmed to x1 FPGA Manager Altera Corporation Send Feedback...
Page 156 32-bit Passive Parallel with Slow Power on Reset Delay; With AES Encryption; No Data Compression. CDRATIO must be programmed to x4 32-bit Passive Parallel with Slow Power on Reset Delay; AES Optional; With Data FPGA Manager Altera Corporation Send Feedback...
Page 157 FPGA in Configuration Phase FPGA in Initialization Phase. In CVP configu‐ ration, this state indicates IO configuration has completed. FPGA in User Mode FPGA state has not yet been determined. This only occurs briefly after reset. FPGA Manager Altera Corporation Send Feedback...
Page 158 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved cfgwd axicf cdratio prreq confd nstat nconf onepu uspul igpul RW 0x0 RW 0x0 FPGA Manager Altera Corporation Send Feedback...
Page 159 FPGA if CTRL.EN is 1. Value Description Incoming AXI data transfers will be ignored. DCLK will not toggle during data transfer. AXI data transfer to CB is active. DCLK will toggle during data transfer. FPGA Manager Altera Corporation Send Feedback...
Page 160 Don't pull-down CONF_DONE input to the Pull-down CONF_DONE input to the CB. Pulls down nSTATUS input to the CB nstatuspull Value Description Don't pull-down nSTATUS input to the CB. Pull-down nSTATUS input to the CB. FPGA Manager Altera Corporation Send Feedback...
Page 161 CLKUSR pin. In the case that DCLK is requested, the DCLKCNT register is used by software to control DCLK during the initialization phase. Software should poll the DCLKSTAT.DCNTDONE write one to clear register to be set when the correct number of DCLKs FPGA Manager Altera Corporation Send Feedback...
Page 162 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. FPGA Manager Altera Corporation Send Feedback...
Page 163 Provides a low-latency, low-performance, and simple way to drive general-purpose signals to the FPGA fabric. Module Instance Base Address Register Address fpgamgrregs 0xFF706000 0xFF706010 Offset: 0x10 Access: Bit Fields value RW 0x0 value RW 0x0 FPGA Manager Altera Corporation Send Feedback...
Page 164 If the FPGA is not in User Mode, the value of this field is undefined. misci Provides a low-latency, low-performance, and simple way to read specific handshaking signals driven from the FPGA fabric. Module Instance Base Address Register Address fpgamgrregs 0xFF706000 0xFF706018 FPGA Manager Altera Corporation Send Feedback...
Page 165 The Configuration Monitor allows software to poll or be interrupted by changes in the FPGA state. The Configuration Monitor is an instantiation of a Synopsys GPIO. Only registers relevant to the MON operation are shown. The GPIO inputs are connected to the following signals: FPGA Manager Altera Corporation Send Feedback...
Page 166 The unmasked status can be read as well as the resultant status after masking. gpio_inttype_level on page 4-30 The interrupt level register defines the type of interrupt (edge or level) for each GPIO input. FPGA Manager Altera Corporation Send Feedback...
Page 167 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. FPGA Manager Altera Corporation Send Feedback...
Page 168 Enables interrupt generation for nSTATUS Pin Value Description Disable Interrupt Enable Interrupt Enables interrupt generation for nCONFIG Pin Value Description Disable Interrupt Enable Interrupt Enables interrupt generation for PR_DONE Value Description Disable Interrupt Enable Interrupt FPGA Manager Altera Corporation Send Feedback...
Page 169 Enable Interrupt Enables interrupt generation for CRC_ERROR Value Description Disable Interrupt Enable Interrupt Enables interrupt generation for INIT_DONE Value Description Disable Interrupt Enable Interrupt Enables interrupt generation for CONF_DONE Value Description Disable Interrupt Enable Interrupt FPGA Manager Altera Corporation Send Feedback...
Page 170 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 FPGA Manager Altera Corporation Send Feedback...
Page 171 Controls whether an interrupt for nCONFIG Pin can generate an interrupt to the interrupt controller by not masking it. The unmasked status can be read as well as the resultant status after masking. Value Description Unmask Interrupt Mask Interrupt FPGA Manager Altera Corporation Send Feedback...
Page 172 Controls whether an interrupt for CVP_CONF_ DONE can generate an interrupt to the interrupt controller by not masking it. The unmasked status can be read as well as the resultant status after masking. Value Description Unmask Interrupt Mask Interrupt FPGA Manager Altera Corporation Send Feedback...
Page 173 Value Description Unmask Interrupt Mask Interrupt gpio_inttype_level The interrupt level register defines the type of interrupt (edge or level) for each GPIO input. Module Instance Base Address Register Address fpgamgrregs 0xFF706000 0xFF706838 FPGA Manager Altera Corporation Send Feedback...
Page 174 Controls whether the level of CONF_DONE Pin or an edge on CONF_DONE Pin generates an interrupt. Value Description Level-sensitive Edge-sensitive Controls whether the level of nSTATUS Pin or an edge on nSTATUS Pin generates an interrupt. Value Description Level-sensitive Edge-sensitive FPGA Manager Altera Corporation Send Feedback...
Page 175 Controls whether the level of PR_READY or an edge on PR_READY generates an interrupt. Value Description Level-sensitive Edge-sensitive Controls whether the level of CVP_CONF_DONE or an edge on CVP_CONF_DONE generates an interrupt. Value Description Level-sensitive Edge-sensitive FPGA Manager Altera Corporation Send Feedback...
Page 176 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. FPGA Manager Altera Corporation Send Feedback...
Page 177 Controls the polarity of edge or level sensitivity for nSTATUS Pin Value Description Active low Active high Controls the polarity of edge or level sensitivity for nCONFIG Pin Value Description Active low Active high FPGA Manager Altera Corporation Send Feedback...
Page 178 Active high Controls the polarity of edge or level sensitivity for CRC_ERROR Value Description Active low Active high Controls the polarity of edge or level sensitivity for INIT_DONE Value Description Active low Active high FPGA Manager Altera Corporation Send Feedback...
Page 179 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RO 0x0 FPGA Manager Altera Corporation Send Feedback...
Page 180 Description Inactive Active Indicates whether nCONFIG Pin has an active interrupt or not (after masking). Value Description Inactive Active Indicates whether PR_DONE has an active interrupt or not (after masking). Value Description Inactive Active FPGA Manager Altera Corporation Send Feedback...
Page 181 Value Description Inactive Active Indicates whether INIT_DONE has an active interrupt or not (after masking). Value Description Inactive Active Indicates whether CONF_DONE has an active interrupt or not (after masking). Value Description Inactive Active FPGA Manager Altera Corporation Send Feedback...
Page 182 Bit Fields Reserved Reserved RO 0x0 gpio_raw_intstatus Fields Name Description Access Reset Indicates whether FPGA_POWER_ON has an active interrupt or not (before masking). Value Description Inactive Active FPGA Manager Altera Corporation Send Feedback...
Page 183 Value Description Inactive Active Indicates whether PR_ERROR has an active interrupt or not (before masking). Value Description Inactive Active Indicates whether PR_READY has an active interrupt or not (before masking). Value Description Inactive Active FPGA Manager Altera Corporation Send Feedback...
Page 184 Indicates whether nSTATUS has an active interrupt or not (before masking). Value Description Inactive Active gpio_porta_eoi This register is written by software to clear edge interrupts generated by each individual GPIO input. This register always reads back as zero. FPGA Manager Altera Corporation Send Feedback...
Page 185 Used by software to clear an CONF_DONE Pin edge interrupt. Value Description No interrupt clear Clear interrupt Used by software to clear an nSTATUS Pin edge interrupt. Value Description No interrupt clear Clear interrupt FPGA Manager Altera Corporation Send Feedback...
Page 186 Clear interrupt Used by software to clear an CVP_CONF_DONE edge interrupt. Value Description No interrupt clear Clear interrupt Used by software to clear an CRC_ERROR edge interrupt. Value Description No interrupt clear Clear interrupt FPGA Manager Altera Corporation Send Feedback...
Page 187 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RO 0x0 FPGA Manager Altera Corporation Send Feedback...
Page 188 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. FPGA Manager Altera Corporation Send Feedback...
Page 189 Value Description No synchronization to l4_mp_clk Synchronize to l4_mp_clk gpio_ver_id_code GPIO Component Version Module Instance Base Address Register Address fpgamgrregs 0xFF706000 0xFF70686C Offset: 0x86C Access: Bit Fields gpio_ver_id_code RO 0x3230382A gpio_ver_id_code RO 0x3230382A FPGA Manager Altera Corporation Send Feedback...
Page 190 Reset 19:15 Specifies the width of GPIO Port D. Ignored because encoded_id_pwidth_d there is no Port D in the GPIO. Value Description Width (less 1) of 8 bits Width (less 1) of 12 bits FPGA Manager Altera Corporation Send Feedback...
Page 191 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. FPGA Manager Altera Corporation Send Feedback...
Page 192 The value of this field is fixed to not allow debouncing debounce of the Port A signals. Value Description Debounce is Disabled The value of this field is fixed to allow interrupts on porta_intr Port A. Value Description Port A Interrupts Enabled FPGA Manager Altera Corporation Send Feedback...
Page 193 The value of this register is fixed at one port (Port A). num_ports Value Description Number of GPIO Ports = 1 Fixed to support an APB data bus width of 32-bits. apb_data_width Value Description APB Data Width = 32-bits FPGA Manager Altera Corporation Send Feedback...
Page 194: Document Revision History
Minor updates. June 2012 Updated the FPGA configuration section. May 2012 • Updated the configuration schemes table. • Updated the FPGA configuration section. • Added address map and register definitions section. January 2012 Initial release. FPGA Manager Altera Corporation Send Feedback...
Page 195: System Manager
• Sends error correction code (ECC) enable signals to all HPS modules with ECC-protected RAM. • Provides the capability to inject errors during testing in the MPU L2 ECC-protected RAM. 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos ©...
Page 196: System Manager Block Diagram And System Integration
ECC & Parity Generic Interrupt Interrupts Controller Register Slave Memory-Mapped Interface Control Signals CSRs Other Modules ECC Control and Status Signals Modules with ECC RAM FPGA JTAG Control HPS BSEL pins FPGA Control FPGA Block Fabric System Manager Altera Corporation Send Feedback...
Page 197: Functional Description Of The System Manager
Each module in the HPS has its own CSRs, providing access to the internal state of the module. The system manager provides registers for additional module control and monitoring. To fully control each module, System Manager Altera Corporation Send Feedback...
Page 198: Dma Controller
Note: Register bits must be accessed only when the master interface is guaranteed to be in an inactive state. Related Information NAND Flash Controller • on page 13-1 System Manager Address Map and Register Definitions • on page 5-9 System Manager Altera Corporation Send Feedback...
Page 199 • CAN Controller on page 25-1 http://www.altera.com/literature/hb/cyclone-v/hps.html • For more information on the System Manger's registers, refer to the Cyclone V SoC HPS Address Map and Register Definitions page. EMAC You can program the register to select either from the Clock Manager or...
Page 200: Boot Rom Code
Registers in the system manager also control whether the boot ROM code configures the I/O pins used during the boot process after a warm reset. Set the warm reset configure I/Os for boot pins bit ) of the register to enable or disable this control. warmrstcfgio ctrl System Manager Altera Corporation Send Feedback...
Page 201 ROM. The enable safe mode warm reset update bit controls whether the wait state bit is updated during a warm reset. L3 Interconnect The System Manager provides remap bits to the L3 interconnect. These bits can remap the Boot ROM and the On-chip RAM. System Manager Altera Corporation Send Feedback...
Page 202: Fpga Interface Enables
Note: The injection request is edge-sensitive, meaning that the request is latched on 0 to 1 transitions on the injection bit. The next time a write operation occurs, the data will be corrupted, containing System Manager Altera Corporation Send Feedback...
Page 203: Preloader Handoff Information
Introduction to the Hard Processor System • on page 1-1 The base addresses of all modules are also listed in the Introduction to the Hard Processor System chapter in the Cyclone V Device Handbook, Volume 3. http://www.altera.com/literature/hb/cyclone-v/hps.html • System Manager Module Address Map...
Page 204 Reset Value Description VIO Control Register vioctrl on page 5-38 0x40 HIO Control Register hioctrl on page 5-39 0x50 0xE0 Source Register on page 5-42 0x54 Hardware Control Register hwctrl on page 5-42 0x58 System Manager Altera Corporation Send Feedback...
Page 205 0xC4 5-56 Preloader (initial software) State initswstate on page 0xC8 Register 5-57 Preloader (initial software) Last initswlastld on page 0xCC Image Loaded Register 5-57 Boot ROM Software State Register bootromswstate 0xD0 page 5-58 System Manager Altera Corporation Send Feedback...
Page 206 5- 0x10C Register NAND Flash Controller Register Group Register Offset Width Acces Reset Value Description Bootstrap Control Register bootstrap on page 5- 0x110 NAND L3 Master AxCACHE l3master on page 5- 0x114 Register System Manager Altera Corporation Send Feedback...
Page 207 Register Offset Width Acces Reset Value Description emac0_tx_clk Mux Selection EMACIO0 on page 5-107 0x400 Register emac0_tx_d0 Mux Selection EMACIO1 on page 5-108 0x404 Register emac0_tx_d1 Mux Selection EMACIO2 on page 5-109 0x408 Register System Manager Altera Corporation Send Feedback...
Page 208 Register emac1_rx_d1 Mux Selection EMACIO19 0x44C Register sdmmc_cmd Mux Selection FLASHIO0 on page 5- 0x450 Register sdmmc_pwren Mux Selection FLASHIO1 on page 5- 0x454 Register sdmmc_d0 Mux Selection FLASHIO2 on page 5- 0x458 Register System Manager Altera Corporation Send Feedback...
Page 209 Mux Selection Register GENERALIO7 on page 5- 0x49C trace_d7 Mux Selection Register GENERALIO8 on page 5- 0x4A0 spim0_clk Mux Selection Register GENERALIO9 on page 5- 0x4A4 spim0_mosi Mux Selection GENERALIO10 on page 0x4A8 Register 5-134 System Manager Altera Corporation Send Feedback...
Page 210 Mux Selection Register MIXED1IO2 0x508 nand_re Mux Selection Register MIXED1IO3 0x50C nand_rb Mux Selection Register MIXED1IO4 0x510 nand_dq0 Mux Selection Register MIXED1IO5 0x514 nand_dq1 Mux Selection Register MIXED1IO6 0x518 nand_dq2 Mux Selection Register MIXED1IO7 0x51C System Manager Altera Corporation Send Feedback...
Page 211 Mux Selection MIXED2IO2 on page 5- 0x560 Register emac1_tx_d3 Mux Selection MIXED2IO3 on page 5- 0x564 Register emac1_rx_clk Mux Selection MIXED2IO4 on page 5- 0x568 Register emac1_rx_ctl Mux Selection MIXED2IO5 on page 5- 0x56C Register System Manager Altera Corporation Send Feedback...
Page 212 Selection Register GPIO/LoanIO 63 Input Mux GPLINMUX63 on page 5- 0x5B4 Selection Register GPIO/LoanIO 64 Input Mux GPLINMUX64 on page 5- 0x5B8 Selection Register GPIO/LoanIO 65 Input Mux GPLINMUX65 on page 5- 0x5BC Selection Register System Manager Altera Corporation Send Feedback...
Page 213 GPIO/LoanIO 12 Output/Output GPLMUX12 on page 5- 0x604 Enable Mux Selection Register GPIO/LoanIO 13 Output/Output GPLMUX13 on page 5- 0x608 Enable Mux Selection Register GPIO/LoanIO 14 Output/Output GPLMUX14 on page 5- 0x60C Enable Mux Selection Register System Manager Altera Corporation Send Feedback...
Page 214 GPIO/LoanIO 32 Output/Output GPLMUX32 on page 5- 0x654 Enable Mux Selection Register GPIO/LoanIO 33 Output/Output GPLMUX33 on page 5- 0x658 Enable Mux Selection Register GPIO/LoanIO 34 Output/Output GPLMUX34 on page 5- 0x65C Enable Mux Selection Register System Manager Altera Corporation Send Feedback...
Page 215 GPIO/LoanIO 52 Output/Output GPLMUX52 on page 5- 0x6A4 Enable Mux Selection Register GPIO/LoanIO 53 Output/Output GPLMUX53 on page 5- 0x6A8 Enable Mux Selection Register GPIO/LoanIO 54 Output/Output GPLMUX54 on page 5- 0x6AC Enable Mux Selection Register System Manager Altera Corporation Send Feedback...
Page 216 (HPS Pins or FPGA Interface) 5-232 Select source for I2C0 signals I2C0USEFPGA on page 0x704 (HPS Pins or FPGA Interface) 5-232 Select source for RGMII0 signals RGMII0USEFPGA on page 0x714 (HPS Pins or FPGA Interface) 5-233 System Manager Altera Corporation Send Feedback...
Page 217 Register Address sysmgr 0xFFD08000 0xFFD08000 Offset: Access: Bit Fields RO 0x0 RO 0x1 siliconid1 Fields Name Description Access Reset 31:16 Silicon ID Value Description HPS in Cyclone V and Arria V SoC FPGA devices System Manager Altera Corporation Send Feedback...
Page 218 L4 watchdogs. Note that the watchdogs built into the MPU automatically are paused when their associated CPU enters debug mode. Only reset by a cold reset. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08010 System Manager Altera Corporation Send Feedback...
Page 219 CPUs Pause normal operation only if CPU0 is in debug mode Pause normal operation only if CPU1 is in debug mode Pause normal operation if CPU0 or CPU1 is in debug mode System Manager Altera Corporation Send Feedback...
Page 220 RO 0x0 RO 0x0 RO 0x0 bootinfo Fields Name Description Access Reset Specifies the sampled value of the HPS CSEL pins. pincsel The value of HPS CSEL pins are sampled upon deassertion of cold reset. System Manager Altera Corporation Send Feedback...
Page 221 SD/MMC device clock is osc1_clk divided by 2, NAND device operation is osc1_clk multiplied by 10/25 QSPI device clock is osc1_clk multiplied by 2, SD/MMC device clock is osc1_clk divided by 4, NAND device operation is osc1_clk multiplied by 5/25 System Manager Altera Corporation Send Feedback...
Page 222 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved dualcore RO 0x0 System Manager Altera Corporation Send Feedback...
Page 223 Bit Fields Reserved btac_1 btac_ ghb_1 ghb_0 ictag ictag icdat icdat maint maint dcout dcout dctag dctag dcdat dcdata_0 lb_1 lb_0 er_1 er_0 RW 0x0 RW 0x0 System Manager Altera Corporation Send Feedback...
Page 224 If 1, injecting parity error to Data Cache Outer dcouter_0 RAM.The field array index corresponds to the CPU index. If 1, injecting parity error to Data Cache Tag dctag_1 RAM.The field array index corresponds to the CPU index. System Manager Altera Corporation Send Feedback...
Page 225 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 226 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 227 Trace interface is disabled. HPS debug logic cannot send trace data to the FPGA fabric. Trace interface is enabled. Other registers in the HPS debug logic must be programmmed to actually send trace data to the FPGA fabric. System Manager Altera Corporation Send Feedback...
Page 228 HPS JTAG operation. Value Description JTAG enable interface is disabled. Logic in the FPGA fabric cannot disable the HPS JTAG. JTAG enable interface is enabled. Logic in the FPGA fabric can disable the HPS JTAG. System Manager Altera Corporation Send Feedback...
Page 229 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved emac_ emac_ Reserved System Manager Altera Corporation Send Feedback...
Page 230 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 231 Contains register field to choose between software state machine (vioctrl array index [1] register) or hardware state machine in the Freeze Controller as the freeze signal source for VIO channel 1. All fields are only reset by a cold reset (ignore warm reset). System Manager Altera Corporation Send Feedback...
Page 232 Bit Fields Reserved Reserved slew wkpul trist busho RW 0x0 vioctrl Fields Name Description Access Reset Controls IO slew-rate slew Value Description Slew-rate forced to slow. Slew-rate controlled by IO configuration. System Manager Altera Corporation Send Feedback...
Page 233 (ignore warm reset). The following equation determines when the weak pullup resistor is enabled: enabled = ~wkpullup | (CFF & cfg & tristate) where CFF is the value of weak pullup as set by IO configuration Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08050 Offset: 0x50 Access: System Manager Altera Corporation Send Feedback...
Page 234 IO configuration in OCT calibration block. Controls IO and DQS reset. regrst Value Description No reset. Resets all IO registers and DQS registers. Controls OCT reset. octrst Value Description No reset. Resets registers in the OCT. System Manager Altera Corporation Send Feedback...
Page 235 Disable bus hold circuit. Bus hold circuit controlled by IO configura‐ tion. Controls IO configuration Value Description Disable IO configuration (forced to a safe value). Enables IO configuration as previously configured by software using the Scan Manager. System Manager Altera Corporation Send Feedback...
Page 236 Activate freeze or thaw operations on VIO channel 1 (HPS IO bank 2 and bank 3) and monitor for completeness and the current state. These fields interact with the hardware state machine in the Freeze Controller. These fields can be accessed independent of the value of SRC1.VIO1 although they only have System Manager Altera Corporation Send Feedback...
Page 237 Frozen state. I/O configuration is ignored. Instead, I/Os are in tri-state mode with a weak pull-up. Scan Manager can be used to configure the I/Os while they are frozen. Transitioning from frozen state to thawed state. System Manager Altera Corporation Send Feedback...
Page 238 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 239 This is sampled by an EMAC module when it exits from reset. The associated enum defines the allowed values. The field array index corresponds to the EMAC index. Value Description Select GMII/MII PHY interface Select RGMII PHY interface Select RMII PHY interface System Manager Altera Corporation Send Feedback...
Page 240 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved awcache_1 awcache_0 arcache_1 arcache_0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 System Manager Altera Corporation Send Feedback...
Page 241 Cacheable write-back, allocate on reads only. Reserved. Reserved. Cacheable write-through, allocate on writes only. Cacheable write-back, allocate on writes only. Reserved. Reserved. Cacheable write-through, allocate on both reads and writes. Cacheable write-back, allocate on both reads and writes. System Manager Altera Corporation Send Feedback...
Page 242 Cacheable write-back, allocate on reads only. Reserved. Reserved. Cacheable write-through, allocate on writes only. Cacheable write-back, allocate on writes only. Reserved. Reserved. Cacheable write-through, allocate on both reads and writes. Cacheable write-back, allocate on both reads and writes. System Manager Altera Corporation Send Feedback...
Page 243 Cacheable write-back, allocate on reads only. Reserved. Reserved. Cacheable write-through, allocate on writes only. Cacheable write-back, allocate on writes only. Reserved. Reserved. Cacheable write-through, allocate on both reads and writes. Cacheable write-back, allocate on both reads and writes. System Manager Altera Corporation Send Feedback...
Page 244 Controls the security state of a peripheral request interface. Sampled by the DMA controller when it exits from reset. These register bits should be updated during system initialization prior to removing the DMA controller from reset. They may not be changed dynamically during DMA operation. System Manager Altera Corporation Send Feedback...
Page 245 Specifies the security state of the DMA manager mgrnonsecure thread. 0 = assigns DMA manager to the Secure state. 1 = assigns DMA manager to the Non-secure state. Sampled by the DMA controller when it exits from reset. System Manager Altera Corporation Send Feedback...
Page 246 Controls the security state of a peripheral request interface. Sampled by the DMA controller when it exits from reset. These register bits should be updated during system initialization prior to removing the DMA controller from reset. They may not be changed dynamically during DMA operation. System Manager Altera Corporation Send Feedback...
Page 247 The contents of these registers have no impact on the state of the click here. HPS hardware. For more information on the registers handoff Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08080 System Manager Altera Corporation Send Feedback...
Page 248 Registers used by the Boot ROM code to support booting from the On-chip RAM on a warm reset. All these registers must be written by user software before a warm reset occurs to make use of this feature. ctrl Contains information used to control Boot ROM code. System Manager Altera Corporation Send Feedback...
Page 249 It is up to user software to enable this field if it wants a different behavior. Value Description Boot ROM code will not configure IOs used by boot after a warm reset Boot ROM code will configure IOs used by boot after a warm reset System Manager Altera Corporation Send Feedback...
Page 250 0xFFD08000 0xFFD080C4 Offset: 0xC4 Access: Bit Fields value RW 0x0 value RW 0x0 cpu1startaddr Fields Name Description Access Reset 31:0 Address for CPU1 to start executing at after coming value out of reset. System Manager Altera Corporation Send Feedback...
Page 251 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 252 Registers used by the Boot ROM code to support booting from the On-chip RAM on a warm reset. All these registers must be written by user software before a warm reset occurs to make use of this feature. System Manager Altera Corporation Send Feedback...
Page 253 Length of region in On-chip RAM for CRC validation. enable Enables or disables the warm reset from On-chip RAM feature. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD080E0 Offset: 0xE0 Access: Bit Fields magic RW 0x0 magic RW 0x0 System Manager Altera Corporation Send Feedback...
Page 254 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved offset RW 0x0 System Manager Altera Corporation Send Feedback...
Page 255 On-chip RAM, the Boot ROM won't boot from the On-chip RAM. The length must be an integer multiple of 4. The Boot ROM code will clear the top 16 bits and the bottom 2 bits. System Manager Altera Corporation Send Feedback...
Page 256 0xFFFF when it reads this register, but does not change the contents of this register. Length of region in On-chip RAM for CRC validation. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD080F0 Offset: 0xF0 Access: System Manager Altera Corporation Send Feedback...
Page 257 Controls behavior of Boot ROM hardware. All fields are only reset by a cold reset (ignore warm reset). ctrl Controls behavior of Boot ROM hardware. All fields are only reset by a cold reset (ignore warm reset). Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08100 Offset: 0x100 System Manager Altera Corporation Send Feedback...
Page 258 No wait states are applied to the Boom ROM's read operation. A single wait state is applied to the Boot ROM's read operation. SDMMC Controller Group Register Descriptions Registers related to SDMMC Controller which aren't located inside the SDMMC itself. System Manager Altera Corporation Send Feedback...
Page 259 If 1, cclk_in_sample is driven by fb_clk_in. No phase shifting is provided internally on cclk_in_sample. Note: Using the feedback clock (setting this bit to 1) is not a supported use model. System Manager Altera Corporation Send Feedback...
Page 260 They may not be changed dynamically during peripheral operation All fields are reset by a cold or warm reset. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD0810C Offset: 0x10C Access: System Manager Altera Corporation Send Feedback...
Page 261 Controls the L3 master ARCACHE and AWCACHE AXI signals. These register bits should be updated only during system initialization prior to removing the peripheral from reset. They may not be changed dynamically during peripheral operation All fields are reset by a cold or warm reset. System Manager Altera Corporation Send Feedback...
Page 262 If 1, NAND device has a 512 byte page size. page512 If 1, inhibits NAND Flash Controller from noinit performing initialization when coming out of reset. Instead, software must program all registers pertaining to device parameters like page size, width, etc. System Manager Altera Corporation Send Feedback...
Page 263 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved awcache_0 arcache_0 RW 0x0 RW 0x0 System Manager Altera Corporation Send Feedback...
Page 264 Cacheable write-back, allocate on reads only. Reserved. Reserved. Cacheable write-through, allocate on writes only. Cacheable write-back, allocate on writes only. Reserved. Reserved. Cacheable write-through, allocate on both reads and writes. Cacheable write-back, allocate on both reads and writes. System Manager Altera Corporation Send Feedback...
Page 265 Controls the L3 master HPROT AHB-Lite signal. These register bits should be updated only during system initialization prior to removing the peripheral from reset. They may not be changed dynamically during peripheral operation All fields are reset by a cold or warm reset. System Manager Altera Corporation Send Feedback...
Page 266 If 1, L3 master accesses for the USB modules are hprotpriv_1 privileged. The field array index corresponds to the USB index. If 1, L3 master accesses for the USB modules are hprotpriv_0 privileged. The field array index corresponds to the USB index. System Manager Altera Corporation Send Feedback...
Page 267 This register is used to enable ECC on the EMAC0 RAM. ECC errors can be injected into the write path using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only reset by a cold reset (ignores warm reset). System Manager Altera Corporation Send Feedback...
Page 268 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 269 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 270 This register contains interrupt status of the ECC single/double bit error. Only reset by a cold reset (ignores warm reset). Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08148 Offset: 0x148 Access: System Manager Altera Corporation Send Feedback...
Page 271 This register contains interrupt status of the ECC single/double bit error. Only reset by a cold reset (ignores warm reset). Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD0814C System Manager Altera Corporation Send Feedback...
Page 272 This register is used to enable ECC on the EMAC0 RAM. ECC errors can be injected into the write path using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only reset by a cold reset (ignores warm reset). System Manager Altera Corporation Send Feedback...
Page 273 This bit is an interrupt status bit for EMAC0 TXFIFO txfifoserr RAM ECC single, correctable error. It is set by hardware when single, correctable error occurs in EMAC0 TXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt status. System Manager Altera Corporation Send Feedback...
Page 274 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved rxfif rxfif txfif txfif rxfif rxfif txfif txfif oderr oserr oderr oserr oinjd oinjs oinjd oinjs RW 0x0 System Manager Altera Corporation Send Feedback...
Page 275 EMAC1 TXFIFO RAM. Changing this bit from zero to one injects a single, txfifoinjs correctable error into the EMAC1 TXFIFO RAM. This only injects one error into the EMAC1 TXFIFO RAM. Enable ECC for EMAC1 RAM System Manager Altera Corporation Send Feedback...
Page 276 DMA RAM. Changing this bit from zero to one injects a single, injs correctable error into the DMA RAM. This only injects one error into the DMA RAM. System Manager Altera Corporation Send Feedback...
Page 277 This bit is an interrupt status bit for CAN0 RAM ECC serr single, correctable error. It is set by hardware when single, correctable error occurs in CAN0 RAM. Software needs to write 1 into this bit to clear the interrupt status. System Manager Altera Corporation Send Feedback...
Page 278 This bit is an interrupt status bit for CAN1 RAM ECC derr double bit, non-correctable error. It is set by hardware when double bit, non-correctable error occurs in CAN1 RAM. Software needs to write 1 into this bit to clear the interrupt status. System Manager Altera Corporation Send Feedback...
Page 279 Bit Fields Reserved Reserved rdfif rdfif wrfif wrfif eccbu eccbu rdfif rdfif wrfif wrfif eccbu eccbu oderr oserr oderr oserr fderr fserr oinjd oinjs oinjd oinjs finjd finjs RW 0x0 System Manager Altera Corporation Send Feedback...
Page 280 This only injects one double bit error into the NAND RDFIFO RAM. Changing this bit from zero to one injects a single, rdfifoinjs correctable error into the NAND RDFIFO RAM. This only injects one error into the NAND RDFIFO RAM. System Manager Altera Corporation Send Feedback...
Page 281 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved derr serr injd injs RW 0x0 System Manager Altera Corporation Send Feedback...
Page 282 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 283 SDMMC RAM at Port B. Changing this bit from zero to one injects a single, injsportb correctable error into the SDMMC RAM at Port B. This only injects one error into the SDMMC RAM at Port B. System Manager Altera Corporation Send Feedback...
Page 284 This register is used to control the peripherals connected to emac0_rx_d0 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 285 This register is used to control the peripherals connected to sdmmc_d0 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 286 This register is used to control the peripherals connected to trace_d0 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 287 This register is used to control the peripherals connected to spim0_ss0 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 288 This register is used to control the peripherals connected to nand_dq7 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 289 This register is used to control the peripherals connected to emac1_mdc Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 290 Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/ LoanIO 52. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 291 Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/ LoanIO 63. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 292 Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 293 Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 294 Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 295 Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 296 Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 297 Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 298 Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 299 Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 300 Selection between HPS Pins and FPGA Interface for I2C3 signals. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 301 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 302 Pin is connected to GPIO/LoanIO number 1. 1 : Pin is connected to Peripheral signal not applicable. 2 : Pin is connected to Peripheral signal USB1.D0. 3 : Pin is connected to Peripheral signal RGMII0.TXD0. System Manager Altera Corporation Send Feedback...
Page 303 (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD0840C Offset: 0x40C Access: System Manager Altera Corporation Send Feedback...
Page 304 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 305 Pin is connected to GPIO/LoanIO number 5. 1 : Pin is connected to Peripheral signal not applicable. 2 : Pin is connected to Peripheral signal USB1.D4. 3 : Pin is connected to Peripheral signal RGMII0.RXD0. System Manager Altera Corporation Send Feedback...
Page 306 NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD0841C Offset: 0x41C Access: System Manager Altera Corporation Send Feedback...
Page 307 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 308 Pin is connected to GPIO/LoanIO number 9. 1 : Pin is connected to Peripheral signal not applicable. 2 : Pin is connected to Peripheral signal not applicable. 3 : Pin is connected to Peripheral signal RGMII0.TX_ CTL. System Manager Altera Corporation Send Feedback...
Page 309 (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD0842C Offset: 0x42C Access: System Manager Altera Corporation Send Feedback...
Page 310 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 311 Pin is connected to GPIO/LoanIO number 13. 1 : Pin is connected to Peripheral signal not applicable. 2 : Pin is connected to Peripheral signal USB1.NXT. 3 : Pin is connected to Peripheral signal RGMII0.RXD3. System Manager Altera Corporation Send Feedback...
Page 312 (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08454 Offset: 0x454 Access: System Manager Altera Corporation Send Feedback...
Page 313 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 314 Pin is connected to GPIO/LoanIO number 39. 1 : Pin is connected to Peripheral signal not applicable. 2 : Pin is connected to Peripheral signal USB0.D3. 3 : Pin is connected to Peripheral signal SDMMC.D1. System Manager Altera Corporation Send Feedback...
Page 315 NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08464 Offset: 0x464 Access: System Manager Altera Corporation Send Feedback...
Page 316 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 317 Pin is connected to GPIO/LoanIO number 43. 1 : Pin is connected to Peripheral signal not applicable. 2 : Pin is connected to Peripheral signal USB0.D7. 3 : Pin is connected to Peripheral signal SDMMC.D7. System Manager Altera Corporation Send Feedback...
Page 318 NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08474 Offset: 0x474 Access: System Manager Altera Corporation Send Feedback...
Page 319 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 320 Pin is connected to GPIO/LoanIO number 47. 1 : Pin is connected to Peripheral signal not applicable. 2 : Pin is connected to Peripheral signal USB0.NXT. 3 : Pin is connected to Peripheral signal SDMMC.D3. System Manager Altera Corporation Send Feedback...
Page 321 NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08484 Offset: 0x484 Access: System Manager Altera Corporation Send Feedback...
Page 322 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 323 Select peripheral signals connected trace_d2. 0 : Pin is connected to GPIO/LoanIO number 51. 1 : Pin is connected to Peripheral signal I2C1.SDA. 2 : Pin is connected to Peripheral signal SPIS0.MISO. 3 : Pin is connected to Peripheral signal TRACE.D2. System Manager Altera Corporation Send Feedback...
Page 324 NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08494 Offset: 0x494 Access: System Manager Altera Corporation Send Feedback...
Page 325 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 326 Select peripheral signals connected trace_d6. 0 : Pin is connected to GPIO/LoanIO number 55. 1 : Pin is connected to Peripheral signal I2C0.SDA. 2 : Pin is connected to Peripheral signal SPIS1.SS0. 3 : Pin is connected to Peripheral signal TRACE.D6. System Manager Altera Corporation Send Feedback...
Page 327 NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD084A4 Offset: 0x4A4 Access: System Manager Altera Corporation Send Feedback...
Page 328 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 329 Pin is connected to GPIO/LoanIO number 59. 1 : Pin is connected to Peripheral signal UART1.CTS. 2 : Pin is connected to Peripheral signal CAN1.RX. 3 : Pin is connected to Peripheral signal SPIM0.MISO. System Manager Altera Corporation Send Feedback...
Page 330 NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD084B4 Offset: 0x4B4 Access: System Manager Altera Corporation Send Feedback...
Page 331 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 332 Select peripheral signals connected i2c0_sda. 0 : Pin is connected to GPIO/LoanIO number 63. 1 : Pin is connected to Peripheral signal SPIM1.CLK. 2 : Pin is connected to Peripheral signal UART1.RX. 3 : Pin is connected to Peripheral signal I2C0.SDA. System Manager Altera Corporation Send Feedback...
Page 333 NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD084C4 Offset: 0x4C4 Access: System Manager Altera Corporation Send Feedback...
Page 334 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 335 Select peripheral signals connected nand_dq3. 0 : Pin is connected to GPIO/LoanIO number 22. 1 : Pin is connected to Peripheral signal USB1.D4. 2 : Pin is connected to Peripheral signal RGMII1.RX_CTL. 3 : Pin is connected to Peripheral signal NAND.dq3. System Manager Altera Corporation Send Feedback...
Page 336 NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08528 Offset: 0x528 Access: System Manager Altera Corporation Send Feedback...
Page 337 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 338 GPIO/LoanIO number 26. 1 : Pin is connected to Peripheral signal not applicable. 2 : Pin is connected to Peripheral signal RGMII1.RXD2. 3 : Pin is connected to Peripheral signal NAND.dq7. System Manager Altera Corporation Send Feedback...
Page 339 NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08538 Offset: 0x538 Access: System Manager Altera Corporation Send Feedback...
Page 340 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 341 Select peripheral signals connected qspi_io1. 0 : Pin is connected to GPIO/LoanIO number 30. 1 : Pin is connected to Peripheral signal USB1.STP. 2 : Pin is connected to Peripheral signal not applicable. 3 : Pin is connected to Peripheral signal QSPI.IO1. System Manager Altera Corporation Send Feedback...
Page 342 NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08548 Offset: 0x548 Access: System Manager Altera Corporation Send Feedback...
Page 343 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 344 GPIO/LoanIO number 34. 1 : Pin is connected to Peripheral signal not applicable. 2 : Pin is connected to Peripheral signal not applicable. 3 : Pin is connected to Peripheral signal QSPI.CLK. System Manager Altera Corporation Send Feedback...
Page 345 (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08558 Offset: 0x558 Access: System Manager Altera Corporation Send Feedback...
Page 346 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 347 Pin is connected to GPIO/LoanIO number 56. 1 : Pin is connected to Peripheral signal SPIS0.MISO. 2 : Pin is connected to Peripheral signal SPIM0.MISO. 3 : Pin is connected to Peripheral signal RGMII1.TXD2. System Manager Altera Corporation Send Feedback...
Page 348 (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08568 Offset: 0x568 Access: System Manager Altera Corporation Send Feedback...
Page 349 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 350 Pin is connected to GPIO/LoanIO number 60. 1 : Pin is connected to Peripheral signal SPIM1.MISO. 2 : Pin is connected to Peripheral signal SPIS1.MISO. 3 : Pin is connected to Peripheral signal RGMII1.RXD2. System Manager Altera Corporation Send Feedback...
Page 351 LoanIO 48. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08578 Offset: 0x578 Access: System Manager Altera Corporation Send Feedback...
Page 352 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 353 Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/ LoanIO 51. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 354 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 355 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 356 Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/ LoanIO 55. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 357 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 358 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 359 Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/ LoanIO 59. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 360 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 361 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 362 Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/ LoanIO 63. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 363 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 364 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 365 Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/ LoanIO 67. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 366 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 367 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 368 Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 369 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 370 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 371 RW 0x0 GPLMUX3 Fields Name Description Access Reset Select source for GPIO/LoanIO 3. 0 : LoanIO 3 controls GPIO/LOANIO[3] output and output enable signals. 1 : GPIO 3 controls GPIO/LOANI[3] output and output enable signals. System Manager Altera Corporation Send Feedback...
Page 372 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD085E8 System Manager Altera Corporation Send Feedback...
Page 373 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 374 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 375 RW 0x0 GPLMUX8 Fields Name Description Access Reset Select source for GPIO/LoanIO 8. 0 : LoanIO 8 controls GPIO/LOANIO[8] output and output enable signals. 1 : GPIO 8 controls GPIO/LOANI[8] output and output enable signals. System Manager Altera Corporation Send Feedback...
Page 376 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD085FC Offset: 0x5FC System Manager Altera Corporation Send Feedback...
Page 377 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 378 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 379 GPLMUX13 Fields Name Description Access Reset Select source for GPIO/LoanIO 13. 0 : LoanIO 13 controls GPIO/LOANIO[13] output and output enable signals. 1 : GPIO 13 controls GPIO/ LOANI[13] output and output enable signals. System Manager Altera Corporation Send Feedback...
Page 380 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08610 Offset: 0x610 System Manager Altera Corporation Send Feedback...
Page 381 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 382 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 383 GPLMUX18 Fields Name Description Access Reset Select source for GPIO/LoanIO 18. 0 : LoanIO 18 controls GPIO/LOANIO[18] output and output enable signals. 1 : GPIO 18 controls GPIO/ LOANI[18] output and output enable signals. System Manager Altera Corporation Send Feedback...
Page 384 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08624 Offset: 0x624 System Manager Altera Corporation Send Feedback...
Page 385 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 386 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 387 GPLMUX23 Fields Name Description Access Reset Select source for GPIO/LoanIO 23. 0 : LoanIO 23 controls GPIO/LOANIO[23] output and output enable signals. 1 : GPIO 23 controls GPIO/ LOANI[23] output and output enable signals. System Manager Altera Corporation Send Feedback...
Page 388 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08638 Offset: 0x638 System Manager Altera Corporation Send Feedback...
Page 389 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 390 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 391 GPLMUX28 Fields Name Description Access Reset Select source for GPIO/LoanIO 28. 0 : LoanIO 28 controls GPIO/LOANIO[28] output and output enable signals. 1 : GPIO 28 controls GPIO/ LOANI[28] output and output enable signals. System Manager Altera Corporation Send Feedback...
Page 392 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD0864C Offset: 0x64C System Manager Altera Corporation Send Feedback...
Page 393 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 394 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 395 GPLMUX33 Fields Name Description Access Reset Select source for GPIO/LoanIO 33. 0 : LoanIO 33 controls GPIO/LOANIO[33] output and output enable signals. 1 : GPIO 33 controls GPIO/ LOANI[33] output and output enable signals. System Manager Altera Corporation Send Feedback...
Page 396 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08660 Offset: 0x660 System Manager Altera Corporation Send Feedback...
Page 397 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 398 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 399 GPLMUX38 Fields Name Description Access Reset Select source for GPIO/LoanIO 38. 0 : LoanIO 38 controls GPIO/LOANIO[38] output and output enable signals. 1 : GPIO 38 controls GPIO/ LOANI[38] output and output enable signals. System Manager Altera Corporation Send Feedback...
Page 400 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08674 Offset: 0x674 System Manager Altera Corporation Send Feedback...
Page 401 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 402 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 403 GPLMUX43 Fields Name Description Access Reset Select source for GPIO/LoanIO 43. 0 : LoanIO 43 controls GPIO/LOANIO[43] output and output enable signals. 1 : GPIO 43 controls GPIO/ LOANI[43] output and output enable signals. System Manager Altera Corporation Send Feedback...
Page 404 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD08688 Offset: 0x688 System Manager Altera Corporation Send Feedback...
Page 405 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 406 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 407 GPLMUX48 Fields Name Description Access Reset Select source for GPIO/LoanIO 48. 0 : LoanIO 48 controls GPIO/LOANIO[48] output and output enable signals. 1 : GPIO 48 controls GPIO/ LOANI[48] output and output enable signals. System Manager Altera Corporation Send Feedback...
Page 408 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD0869C Offset: 0x69C System Manager Altera Corporation Send Feedback...
Page 409 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 410 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 411 GPLMUX53 Fields Name Description Access Reset Select source for GPIO/LoanIO 53. 0 : LoanIO 53 controls GPIO/LOANIO[53] output and output enable signals. 1 : GPIO 53 controls GPIO/ LOANI[53] output and output enable signals. System Manager Altera Corporation Send Feedback...
Page 412 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD086B0 Offset: 0x6B0 System Manager Altera Corporation Send Feedback...
Page 413 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 414 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 415 GPLMUX58 Fields Name Description Access Reset Select source for GPIO/LoanIO 58. 0 : LoanIO 58 controls GPIO/LOANIO[58] output and output enable signals. 1 : GPIO 58 controls GPIO/ LOANI[58] output and output enable signals. System Manager Altera Corporation Send Feedback...
Page 416 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD086C4 Offset: 0x6C4 System Manager Altera Corporation Send Feedback...
Page 417 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 418 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 419 GPLMUX63 Fields Name Description Access Reset Select source for GPIO/LoanIO 63. 0 : LoanIO 63 controls GPIO/LOANIO[63] output and output enable signals. 1 : GPIO 63 controls GPIO/ LOANI[63] output and output enable signals. System Manager Altera Corporation Send Feedback...
Page 420 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD086D8 Offset: 0x6D8 System Manager Altera Corporation Send Feedback...
Page 421 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 422 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 423 GPLMUX68 Fields Name Description Access Reset Select source for GPIO/LoanIO 68. 0 : LoanIO 68 controls GPIO/LOANIO[68] output and output enable signals. 1 : GPIO 68 controls GPIO/ LOANI[68] output and output enable signals. System Manager Altera Corporation Send Feedback...
Page 424 Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. Module Instance Base Address Register Address sysmgr 0xFFD08000 0xFFD086EC Offset: 0x6EC System Manager Altera Corporation Send Feedback...
Page 425 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Manager Altera Corporation Send Feedback...
Page 426 Selection between HPS Pins and FPGA Interface for I2C0 signals. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections. System Manager Altera Corporation Send Feedback...
Page 427 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 428 Bit Fields Reserved Reserved RW 0x0 I2C3USEFPGA Fields Name Description Access Reset Select connection for I2C3. 0 : I2C3 uses HPS Pins. 1 : I2C3 uses the FPGA Inteface. System Manager Altera Corporation Send Feedback...
Page 429 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Manager Altera Corporation Send Feedback...
Page 430 Bit Fields Reserved Reserved RW 0x0 SPIM1USEFPGA Fields Name Description Access Reset Select connection for SPIM1. 0 : SPIM1 uses HPS Pins. 1 : SPIM1 uses the FPGA Inteface. System Manager Altera Corporation Send Feedback...
Page 431: Document Revision History
Document Revision History Table 5-4: Document Revision History Date Version Changes October 2016 2016.10.28 Maintenance release. May 2016 2016.05.03 Maintenance release. November 2015 2015.11.02 Maintenance release. May 2015 2015.05.04 Maintenance release. December 2014 2014.12.15 Maintenance release. System Manager Altera Corporation Send Feedback...
Page 432 • CAN controller section added 2014.02.28 Maintenance release February 2014 December 2013 2013.12.30 Maintenance release. November 2012 Minor updates. May 2012 Added functional description, address map and register definitions sections. January 2012 Initial release. System Manager Altera Corporation Send Feedback...
Page 433: Features Of The Scan Manager
• Drives all the I/O scan chains for HPS I/O banks • Allows the HPS to access the FPGA JTAG TAP controller 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos ©...
Page 434: Scan Manager Block Diagram And System Integration
The signal, register, and field names listed in the table match the names used in the ARM Debug Interface v5 Architecture Specification. Scan Manager Altera Corporation Send Feedback...
Page 435: Arm Jtag-Ap Scan Chains
FPGA JTAG pins are connected to the FPGA JTAG TAP controller. You can configure the system manager to enable the connection, which allows software running on the HPS to communicate with the FPGA JTAG TAP controller. In this case, software Scan Manager Altera Corporation Send Feedback...
Page 436 Note: The HPS JTAG pins and the following HPS I/O pins do not support boundary scan tests (BST): • DDR SDRAM • OSC1/2 • Warm/Cold reset To perform boundary scan testing on HPS I/O pins, use the FPGA JTAG. Related Information Configuring HPS I/O Scan Chains • on page 6-5 Scan Manager Altera Corporation Send Feedback...
Page 437: Functional Description Of The Scan Manager
2016.10.28 Communicating with the JTAG TAP Controller • on page 6-6 Cyclone V Device Handbook Volume 1: Device Interfaces and Integration • For more information about boundary scan tests, refer to the "JTAG Boundary-Scan Testing in Cyclone V Devices" chapter.
Page 438: Communicating With The Jtag Tap Controller
Note: Before connecting or disconnecting the scan chain between the scan manager and the FPGA JTAG TAP controller, ensure that both the FPGA JTAG and scan manager signals are de-asserted. Altera recommends resetting the FPGA JTAG TAP controller using the scan manager's nTRST signal after the scan manager is connected to the controller. Related Information •...
Page 439: Clocks
SPI masters can spi_m_clk support 60 Mbps rates. When the SPI master is running faster than what is supported by the scan manager, the scan manager cannot be used and must be held in reset. Scan Manager Altera Corporation Send Feedback...
Page 440: Resets
Web-based address map and register definitions JTAG-AP Register Name Cross Reference Table To clarify how Altera uses the JTAG-AP, the ARM registers are renamed in the SoC device. The following table cross references the ARM and Altera register names. Table 6-3: JTAG-AP Register Names...
Page 441: Scan Manager Module Registers Address Map
Scan Manager Module Registers Address Map 2016.10.28 Altera Register Name ARM Register Name for writes, for reads fifotriplebyte BWFIFO3 BRFIFO3 for writes, for reads fifoquadbyte BWFIFO4 BRFIFO4 Related Information http://infocenter.arm.com For more information about the ARM JTAG-AP, refer to the DAP Components chapter of the CoreSight SoC Technical Reference Manual , which you can download from the ARM Infocenter website.
Page 442 Response FIFO. Ignore this field. Its value is undefined (may be 0 or 1) ignore . The name of this field in ARM documentation is PORTCONNECTED. Scan Manager Altera Corporation Send Feedback...
Page 443 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved fpgaj Reserved iosca iosca iosca ioscanch nchai nchai nchai ain0 RW 0x0 Scan Manager Altera Corporation Send Feedback...
Page 444 ARM documentation is PSEL1. Value Description Disable scan-chain Enable scan-chain Used to enable or disable I/O Scan-Chain 0 The name ioscanchain0 of this field in ARM documentation is PSEL0. Value Description Disable scan-chain Enable scan-chain Scan Manager Altera Corporation Send Feedback...
Page 445 APB read operation is stalled until the command FIFO is not empty. See the ARM documentation for a description of the read and write values. The name of this register in ARM documentation is BWFIFO2 for writes and BRFIFO2 for reads. Module Instance Base Address Register Address scanmgr 0xFFF02000 0xFFF02014 Scan Manager Altera Corporation Send Feedback...
Page 446 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Scan Manager Altera Corporation Send Feedback...
Page 447 The name of this register in ARM documentation is BWFIFO4 for writes and BRFIFO4 for reads. Module Instance Base Address Register Address scanmgr 0xFFF02000 0xFFF0201C Offset: 0x1C Access: Bit Fields value RW 0x0 value RW 0x0 Scan Manager Altera Corporation Send Feedback...
Page 448: Document Revision History
Update to "Scan Manager Block Diagram and System Integration" section December 2013 2013.12.30 Minor formatting issues November 2012 Added JTAG-AP descriptions. May 2012 Added block diagram and system integration, functional description, and address map and register definitions sections. January 2012 Initial release. Scan Manager Altera Corporation Send Feedback...
Page 449: Features Of The System Interconnect
® • Multiple independent L4 buses 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos © are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants...
Page 450: System Interconnect Block Diagram And System Integration
• Master to Slave Connectivity Matrix on page 7-4 Main Connectivity Matrix • on page 7-3 System Interconnect Architecture The L3 interconnect is a partially-connected switch fabric. Not all masters can access all slaves. System Interconnect Altera Corporation Send Feedback...
Page 451: Main Connectivity Matrix
The following table shows the connectivity matrix of all the master and slave interfaces of the L3 interconnect. For details of the masters and slaves connected to the L3 master peripheral switch and L3 master peripheral (13) switch, refer to "Interconnect Block Diagram". System Interconnect Altera Corporation Send Feedback...
Page 452: Functional Description Of The Interconnect
7-2 Functional Description of the Interconnect Master to Slave Connectivity Matrix The interconnect is a partially-connected crossbar. The following table shows the connectivity matrix of all the master and slave interfaces of the interconnect. System Interconnect Altera Corporation Send Feedback...
Page 453: System Interconnect Address Spaces
• The L3 address space • The MPU address space • The SDRAM address space Available Address Maps The following figure shows the default system interconnect address maps for all masters. The figure is not to scale. System Interconnect Altera Corporation Send Feedback...
Page 454 This region can be configured to access slaves on the HPS-to-FPGA bridge, by using the register. remap The MPU accesses SDRAM through a dedicated port. This region can be configured to access on-chip RAM, by using the register. remap System Interconnect Altera Corporation Send Feedback...
Page 455 0xBFFFFFFF 1 GB HPS-to-FPGA When 0xC0000000 0xFBFFFFFF 960 MB (14) remap.hps2fpga set. Not visible to FPGA-to- HPS bridge. (14) For details about the register, refer to "Bit Fields for Modifying the Memory Map" remap System Interconnect Altera Corporation Send Feedback...
Page 456 Lightweight HPS-to-FPGA Slaves Region The lightweight HPS-to-FPGA slaves provide access to slaves in the FPGA fabric through the lightweight HPS-to-FPGA bridge. Peripherals Region The peripherals region includes slaves connected to the L3 interconnect and L4 buses. System Interconnect Altera Corporation Send Feedback...
Page 457 Peripherals Always visible 0xFF400000 0xFFFCFFFF 12096 KB Boot ROM Always visible 0xFFFD0000 0xFFFEBFFF 112 KB (15) For details about the register, refer to "Bit Fields for Modifying the Memory Map" remap System Interconnect Altera Corporation Send Feedback...
Page 458 The peripherals region is near the top of the address space. The peripheral region includes slaves connected to the L3 interconnect and L4 buses. Boot ROM Region The boot ROM is always mapped near the top of the address space, independent of the boot region contents. System Interconnect Altera Corporation Send Feedback...
Page 459 • MPU master interface • L2 cache master 0 interface • Non-MPU master interfaces • DMA master interface • Master peripheral interfaces • Debug Access Port (DAP) master interface • FPGA-to-HPS bridge master interface System Interconnect Altera Corporation Send Feedback...
Page 460 This bit has no effect on the MPU L3 master. Note that regardless of this setting, the on-chip RAM also always maps to address 0xFFFD0000 for the non-MPU L3 masters. Reserved Must always be 0. System Interconnect Altera Corporation Send Feedback...
Page 461: Master Caching And Buffering Overrides
There is no synchronization between the system manager and the system interconnect, so avoid changing these settings when any of the masters are active. System Interconnect Altera Corporation Send Feedback...
Page 462: Security
Otherwise, the register access results in a bus error, causing a CPU fault. Related Information L3 (NIC-301) GPV Registers Address Map on page 7-23 Information about the GPV registers write_qos System Interconnect Altera Corporation Send Feedback...
Page 463: Cyclic Dependency Avoidance Schemes
Single active slave (SAS) is the same as the SSPID scheme, with an added check for write transactions. SAS ensures that a master cannot issue a new write address until all of the data from the previous write transac‐ tion has been sent. System Interconnect Altera Corporation Send Feedback...
Page 464: System Interconnect Master Properties
L3 master Nonsecur SSPID 1, 8, 9 2, 2, 2, nand_x_clk peripheral 2, 2 switch (16) Each channel has a dedicated FIFO buffer. This allows the channels to function as independent streams. System Interconnect Altera Corporation Send Feedback...
Page 465: Interconnect Slave Properties
Acceptance is based on the number of read, write, and total transactions. (17) The FIFO buffer depth for AXI is based on the AW, AR, R, W, and B channels. For AHB and APB, the depth (18) is based on W, A, and D channels. System Interconnect Altera Corporation Send Feedback...
Page 466 Acceptance is based on the number of read, write, and total transactions. (17) The FIFO buffer depth for AXI is based on the AW, AR, R, W, and B channels. For AHB and APB, the depth (18) is based on W, A, and D channels. System Interconnect Altera Corporation Send Feedback...
Page 467 Acceptance is based on the number of read, write, and total transactions. (17) The FIFO buffer depth for AXI is based on the AW, AR, R, W, and B channels. For AHB and APB, the depth (18) is based on W, A, and D channels. System Interconnect Altera Corporation Send Feedback...
Page 468: Upsizing Data Width Function
Acceptance is based on the number of read, write, and total transactions. (17) The FIFO buffer depth for AXI is based on the AW, AR, R, W, and B channels. For AHB and APB, the depth (18) is based on W, A, and D channels. System Interconnect Altera Corporation Send Feedback...
Page 469: Downsizing Data Width Function
For more information about AXI terms such as , and , refer to the AMBA Network DECERR WRAP INCR Interconnect (NIC-301) Technical Reference Manual, revision r2p3, which you can download from the ARM Infocenter website. System Interconnect Altera Corporation Send Feedback...
Page 470: Lock Support
• On interfaces to all HPS master and slaves except onchip RAM and boot ROM • Between subswitches In addition to buffering, these FIFOs also provide clock domain crossing where masters and slaves operate at a different clock frequency from the switch they connect to. System Interconnect Altera Corporation Send Feedback...
Page 471: System Interconnect Resets
• on page 1-1 The base addresses of all modules are also listed in the Introduction to the Hard Processor chapter. Cyclone V Address Map and Register Definitions • Web-based address map and register definitions L3 (NIC-301) GPV Registers Address Map...
Page 472 SDRAM Data Peripheral Security sdrdata on page 7-59 0xA0 ID Register Group Register Offset Width Acces Reset Value Description Peripheral ID4 Register periph_id_4 on page 0x1FD0 7-60 Peripheral ID0 Register periph_id_0 on page 0x1FE0 7-61 System Interconnect Altera Corporation Send Feedback...
Page 473 Reset Value Description Bus Matrix Issuing Functionality fn_mod_bm_iss on page 0x3008 Modification Register 7-68 L4 MP Register Offset Width Acces Reset Value Description Bus Matrix Issuing Functionality fn_mod_bm_iss on page 0x4008 Modification Register 7-69 System Interconnect Altera Corporation Send Feedback...
Page 474 Issuing Functionality Modification fn_mod on page 7-75 0x8108 Register USB1 Register Offset Width Acces Reset Value Description Bus Matrix Issuing Functionality fn_mod_bm_iss on page 0xA008 Modification Register 7-76 AHB Control Register ahb_cntl on page 7- 0xA044 System Interconnect Altera Corporation Send Feedback...
Page 475 Issuing Functionality Modification fn_mod on page 7-83 0x21108 Register QSPIDATA Register Offset Width Acces Reset Value Description Bus Matrix Issuing Functionality fn_mod_bm_iss on page 0x22008 Modification Register 7-84 AHB Control Register ahb_cntl on page 7- 0x22044 System Interconnect Altera Corporation Send Feedback...
Page 476 7-93 0x25108 Register Boot ROM Register Offset Width Acces Reset Value Description Bus Matrix Issuing Functionality fn_mod_bm_iss on page 0x26008 Modification Register 7-94 Issuing Functionality Modification fn_mod on page 7-95 0x26108 Register System Interconnect Altera Corporation Send Feedback...
Page 477 Register Offset Width Acces Reset Value Description Read Channel QoS Value read_qos on page 7- 0x43100 Write Channel QoS Value write_qos on page 7- 0x43104 Issuing Functionality Modification fn_mod on page 7-105 0x43108 Register System Interconnect Altera Corporation Send Feedback...
Page 478 Write Tidemark wr_tidemark on page 0x46040 7-113 Read Channel QoS Value read_qos on page 7- 0x46100 Write Channel QoS Value write_qos on page 7- 0x46104 Issuing Functionality Modification fn_mod on page 7-115 0x46108 Register System Interconnect Altera Corporation Send Feedback...
Page 479 Issuing Functionality Modification fn_mod on page 7-122 0x49108 Register USB0 Register Offset Width Acces Reset Value Description Functionality Modification AHB fn_mod_ahb on page 7- 0x4A028 Register Read Channel QoS Value read_qos on page 7- 0x4A100 System Interconnect Altera Corporation Send Feedback...
Page 480 The remap bits are not mutually exclusive. Each bit can be set independently and in combinations. Priority for the bits is determined by the bit offset: lower offset bits take precedence over higher offset bits. Module Instance Base Address Register Address l3regs 0xFF800000 0xFF800000 System Interconnect Altera Corporation Send Feedback...
Page 481 Description The HPS2FPGA AXI Bridge is not visible to L3 masters. Accesses to the associated address range return an AXI decode error to the master. The HPS2FPGA AXI Bridge is visible to L3 masters. System Interconnect Altera Corporation Send Feedback...
Page 482 Controls security settings for L4 main peripherals l4sp on page 7-37 Controls security settings for L4 SP peripherals. l4mp on page 7-40 Controls security settings for L4 MP peripherals. l4osc1 on page 7-43 Controls security settings for L4 OSC1 peripherals. System Interconnect Altera Corporation Send Feedback...
Page 483 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 484 Controls whether secure or non-secure masters can spis1 access the SPI Slave 1 slave. Value Description The slave can only be accessed by a secure master. The slave can only be accessed by a secure or non-secure masters. System Interconnect Altera Corporation Send Feedback...
Page 485 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved sptim can1 can0 uart1 uart0 i2c3 i2c2 i2c1 i2c0 sptim sdrregs WO 0x0 System Interconnect Altera Corporation Send Feedback...
Page 486 Controls whether secure or non-secure masters can uart1 access the UART 1 slave. Value Description The slave can only be accessed by a secure master. The slave can only be accessed by a secure or non-secure masters. System Interconnect Altera Corporation Send Feedback...
Page 487 Controls whether secure or non-secure masters can i2c1 access the I2C1 slave. Value Description The slave can only be accessed by a secure master. The slave can only be accessed by a secure or non-secure masters. System Interconnect Altera Corporation Send Feedback...
Page 488 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 489 Controls whether secure or non-secure masters can gpio0 access the GPIO 0 slave. Value Description The slave can only be accessed by a secure master. The slave can only be accessed by a secure or non-secure masters. System Interconnect Altera Corporation Send Feedback...
Page 490 Controls whether secure or non-secure masters can sdmmc access the SDMMC slave. Value Description The slave can only be accessed by a secure master. The slave can only be accessed by a secure or non-secure masters. System Interconnect Altera Corporation Send Feedback...
Page 491 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 492 Controls whether secure or non-secure masters can sysmgr access the System Manager slave. Value Description The slave can only be accessed by a secure master. The slave can only be accessed by a secure or non-secure masters. System Interconnect Altera Corporation Send Feedback...
Page 493 The slave can only be accessed by a secure master. The slave can only be accessed by a secure or non-secure masters. l4spim Controls security settings for L4 SPIM peripherals. Module Instance Base Address Register Address l3regs 0xFF800000 0xFF800018 System Interconnect Altera Corporation Send Feedback...
Page 494 Controls whether secure or non-secure masters can spim1 access the SPI Master 1 slave. Value Description The slave can only be accessed by a secure master. The slave can only be accessed by a secure or non-secure masters. System Interconnect Altera Corporation Send Feedback...
Page 495 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved WO 0x0 System Interconnect Altera Corporation Send Feedback...
Page 496 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved WO 0x0 System Interconnect Altera Corporation Send Feedback...
Page 497 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved WO 0x0 System Interconnect Altera Corporation Send Feedback...
Page 498 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved WO 0x0 System Interconnect Altera Corporation Send Feedback...
Page 499 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved WO 0x0 System Interconnect Altera Corporation Send Feedback...
Page 500 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved WO 0x0 System Interconnect Altera Corporation Send Feedback...
Page 501 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved WO 0x0 System Interconnect Altera Corporation Send Feedback...
Page 502 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved WO 0x0 System Interconnect Altera Corporation Send Feedback...
Page 503 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved WO 0x0 System Interconnect Altera Corporation Send Feedback...
Page 504 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved WO 0x0 System Interconnect Altera Corporation Send Feedback...
Page 505 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved WO 0x0 System Interconnect Altera Corporation Send Feedback...
Page 506 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved WO 0x0 System Interconnect Altera Corporation Send Feedback...
Page 507 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved WO 0x0 System Interconnect Altera Corporation Send Feedback...
Page 508 7-64 Component ID0 comp_id_1 on page 7-64 Component ID1 comp_id_2 on page 7-65 Component ID2 comp_id_3 on page 7-66 Component ID3 periph_id_4 JEP106 continuation code Module Instance Base Address Register Address l3regs 0xFF800000 0xFF801FD0 System Interconnect Altera Corporation Send Feedback...
Page 509 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved pn7to0 RO 0x1 System Interconnect Altera Corporation Send Feedback...
Page 510 Bit Fields Reserved Reserved jep3to0_pn11to8 RO 0xB3 periph_id_1 Fields Name Description Access Reset JEP106[3:0], Part Number [11:8] jep3to0_pn11to8 0xB3 periph_id_2 Peripheral ID2 Module Instance Base Address Register Address l3regs 0xFF800000 0xFF801FE8 Offset: 0x1FE8 Access: System Interconnect Altera Corporation Send Feedback...
Page 511 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved rev_and cust_mod_num RO 0x0 RO 0x0 System Interconnect Altera Corporation Send Feedback...
Page 512 Bit Fields Reserved Reserved preamble RO 0xD comp_id_0 Fields Name Description Access Reset Preamble preamble comp_id_1 Component ID1 Module Instance Base Address Register Address l3regs 0xFF800000 0xFF801FF4 Offset: 0x1FF4 System Interconnect Altera Corporation Send Feedback...
Page 513 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved preamble RO 0x5 System Interconnect Altera Corporation Send Feedback...
Page 514 Interconnect connects to a slave in a module. Offset: 0x2000 L4 MAIN Register Descriptions Registers associated with the L4 MAIN master. This master is used to access the APB slaves on the L4 MAIN bus. Offset: System Interconnect Altera Corporation Send Feedback...
Page 515 Multiple outstanding read transactions Only a single outstanding read transaction L4 SP Register Descriptions Registers associated with the L4 SP master. This master is used to access the APB slaves on the L4 SP bus. System Interconnect Altera Corporation Send Feedback...
Page 516 Reserved Reserved RW 0x0 fn_mod_bm_iss Fields Name Description Access Reset Value Description Multiple outstanding write transactions Only a single outstanding write transaction Value Description Multiple outstanding read transactions Only a single outstanding read transaction System Interconnect Altera Corporation Send Feedback...
Page 517 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 fn_mod_bm_iss Fields Name Description Access Reset Value Description Multiple outstanding write transactions Only a single outstanding write transaction System Interconnect Altera Corporation Send Feedback...
Page 518 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Interconnect Altera Corporation Send Feedback...
Page 519 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 520 Sets the block issuing capability to multiple or single outstanding transactions. fn_mod_bm_iss Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. Module Instance Base Address Register Address l3regs 0xFF800000 0xFF807008 Offset: 0x7008 Access: System Interconnect Altera Corporation Send Feedback...
Page 521 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 522 Sets the block issuing capability to multiple or single outstanding transactions. fn_mod_bm_iss Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. Module Instance Base Address Register Address l3regs 0xFF800000 0xFF808008 Offset: 0x8008 System Interconnect Altera Corporation Send Feedback...
Page 523 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 524 Sets the block issuing capability to one outstanding transaction. fn_mod_bm_iss Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. Module Instance Base Address Register Address l3regs 0xFF800000 0xFF80A008 Offset: 0xA008 Access: System Interconnect Altera Corporation Send Feedback...
Page 525 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 526 Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. fn_mod on page 7-79 Sets the block issuing capability to multiple or single outstanding transactions. fn_mod_bm_iss Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. System Interconnect Altera Corporation Send Feedback...
Page 527 Multiple outstanding read transactions Only a single outstanding read transaction fn_mod Sets the block issuing capability to multiple or single outstanding transactions. Module Instance Base Address Register Address l3regs 0xFF800000 0xFF80B108 Offset: 0xB108 Access: System Interconnect Altera Corporation Send Feedback...
Page 528 Sets the block issuing capability to one outstanding transaction. fn_mod_bm_iss Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. Module Instance Base Address Register Address l3regs 0xFF800000 0xFF820008 System Interconnect Altera Corporation Send Feedback...
Page 529 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 530 Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. fn_mod on page 7-83 Sets the block issuing capability to multiple or single outstanding transactions. fn_mod_bm_iss Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. System Interconnect Altera Corporation Send Feedback...
Page 531 Multiple outstanding read transactions Only a single outstanding read transaction fn_mod Sets the block issuing capability to multiple or single outstanding transactions. Module Instance Base Address Register Address l3regs 0xFF800000 0xFF821108 Offset: 0x21108 Access: System Interconnect Altera Corporation Send Feedback...
Page 532 Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. ahb_cntl on page 7-85 Sets the block issuing capability to one outstanding transaction. fn_mod_bm_iss Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. System Interconnect Altera Corporation Send Feedback...
Page 533 Value Description Multiple outstanding read transactions Only a single outstanding read transaction ahb_cntl Sets the block issuing capability to one outstanding transaction. Module Instance Base Address Register Address l3regs 0xFF800000 0xFF822044 Offset: 0x22044 Access: System Interconnect Altera Corporation Send Feedback...
Page 534 7-87 Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. wr_tidemark on page 7-87 Controls the release of the transaction in the write data FIFO. System Interconnect Altera Corporation Send Feedback...
Page 535 Multiple outstanding write transactions Only a single outstanding write transaction Value Description Multiple outstanding read transactions Only a single outstanding read transaction wr_tidemark Controls the release of the transaction in the write data FIFO. System Interconnect Altera Corporation Send Feedback...
Page 536 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 537 Sets the block issuing capability to multiple or single outstanding transactions. fn_mod_bm_iss Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. Module Instance Base Address Register Address l3regs 0xFF800000 0xFF824008 System Interconnect Altera Corporation Send Feedback...
Page 538 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 539 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Interconnect Altera Corporation Send Feedback...
Page 540 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 541 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 542 Sets the block issuing capability to multiple or single outstanding transactions. fn_mod_bm_iss Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. Module Instance Base Address Register Address l3regs 0xFF800000 0xFF826008 Offset: 0x26008 System Interconnect Altera Corporation Send Feedback...
Page 543 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 544 Sets the block issuing capability to multiple or single outstanding transactions. fn_mod_bm_iss Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. Module Instance Base Address Register Address l3regs 0xFF800000 0xFF827008 System Interconnect Altera Corporation Send Feedback...
Page 545 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 546 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Interconnect Altera Corporation Send Feedback...
Page 547 QoS (Quality of Service) value for the write channel. fn_mod on page 7-103 Sets the block issuing capability to multiple or single outstanding transactions. fn_mod2 Controls bypass merge of upsizing/downsizing. Module Instance Base Address Register Address l3regs 0xFF800000 0xFF842024 Offset: 0x42024 System Interconnect Altera Corporation Send Feedback...
Page 548 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 549 NIC-301 documentation. The L3 Interconnect converts AHB-lite read bursts to AXI single transactions. read_qos QoS (Quality of Service) value for the read channel. Module Instance Base Address Register Address l3regs 0xFF800000 0xFF842100 Offset: 0x42100 System Interconnect Altera Corporation Send Feedback...
Page 550 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Interconnect Altera Corporation Send Feedback...
Page 551 Reserved Reserved RW 0x0 fn_mod Fields Name Description Access Reset Value Description Multiple outstanding write transactions Only a single outstanding write transaction Value Description Multiple outstanding read transactions Only a single outstanding read transaction System Interconnect Altera Corporation Send Feedback...
Page 552 RW 0x0 read_qos Fields Name Description Access Reset QoS (Quality of Service) value for the read channel. A higher value has a higher priority. write_qos QoS (Quality of Service) value for the write channel. System Interconnect Altera Corporation Send Feedback...
Page 553 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 554 7-109 Sets the block issuing capability to multiple or single outstanding transactions. fn_mod_ahb Controls how AHB-lite burst transactions are converted to AXI tranactions. Module Instance Base Address Register Address l3regs 0xFF800000 0xFF844028 System Interconnect Altera Corporation Send Feedback...
Page 555 AXI transactions in accordance with the default behavior as specified in the ARM NIC-301 documentation. The L3 Interconnect converts AHB-lite read bursts to AXI single transactions. read_qos QoS (Quality of Service) value for the read channel. System Interconnect Altera Corporation Send Feedback...
Page 556 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 557 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Interconnect Altera Corporation Send Feedback...
Page 558 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 559 Bit Fields Reserved Reserved RW 0x0 write_qos Fields Name Description Access Reset QoS (Quality of Service) value for the write channel. A higher value has a higher priority. System Interconnect Altera Corporation Send Feedback...
Page 560 Registers associated with the FPGA2HPS AXI Bridge slave interface. This slave is used by the FPGA2HPS AXI Bridge to access slaves attached to the L3/L4 Interconnect. Offset: 0x4000 wr_tidemark on page 7-113 Controls the release of the transaction in the write data FIFO. System Interconnect Altera Corporation Send Feedback...
Page 561 WLAST beat or the write FIFO becomes full. read_qos QoS (Quality of Service) value for the read channel. Module Instance Base Address Register Address l3regs 0xFF800000 0xFF846100 System Interconnect Altera Corporation Send Feedback...
Page 562 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Interconnect Altera Corporation Send Feedback...
Page 563 Reserved Reserved RW 0x0 fn_mod Fields Name Description Access Reset Value Description Multiple outstanding write transactions Only a single outstanding write transaction Value Description Multiple outstanding read transactions Only a single outstanding read transaction System Interconnect Altera Corporation Send Feedback...
Page 564 RW 0x0 read_qos Fields Name Description Access Reset QoS (Quality of Service) value for the read channel. A higher value has a higher priority. write_qos QoS (Quality of Service) value for the write channel. System Interconnect Altera Corporation Send Feedback...
Page 565 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 566 7-120 Sets the block issuing capability to multiple or single outstanding transactions. read_qos QoS (Quality of Service) value for the read channel. Module Instance Base Address Register Address l3regs 0xFF800000 0xFF848100 Offset: 0x48100 System Interconnect Altera Corporation Send Feedback...
Page 567 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Interconnect Altera Corporation Send Feedback...
Page 568 Reserved Reserved RW 0x0 fn_mod Fields Name Description Access Reset Value Description Multiple outstanding write transactions Only a single outstanding write transaction Value Description Multiple outstanding read transactions Only a single outstanding read transaction System Interconnect Altera Corporation Send Feedback...
Page 569 RW 0x0 read_qos Fields Name Description Access Reset QoS (Quality of Service) value for the read channel. A higher value has a higher priority. write_qos QoS (Quality of Service) value for the write channel. System Interconnect Altera Corporation Send Feedback...
Page 570 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 571 7-126 Sets the block issuing capability to multiple or single outstanding transactions. fn_mod_ahb Controls how AHB-lite burst transactions are converted to AXI tranactions. Module Instance Base Address Register Address l3regs 0xFF800000 0xFF84A028 System Interconnect Altera Corporation Send Feedback...
Page 572 AXI transactions in accordance with the default behavior as specified in the ARM NIC-301 documentation. The L3 Interconnect converts AHB-lite read bursts to AXI single transactions. read_qos QoS (Quality of Service) value for the read channel. System Interconnect Altera Corporation Send Feedback...
Page 573 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 574 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 System Interconnect Altera Corporation Send Feedback...
Page 575 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 576 Bit Fields Reserved Reserved RW 0x0 write_qos Fields Name Description Access Reset QoS (Quality of Service) value for the write channel. A higher value has a higher priority. System Interconnect Altera Corporation Send Feedback...
Page 577 Registers associated with the USB1 slave interface. This slave is used by the DMA controller built into the USB1 to access slaves attached to the L3/L4 Interconnect. Offset: 0xa000 fn_mod_ahb on page 7-130 Controls how AHB-lite burst transactions are converted to AXI tranactions. System Interconnect Altera Corporation Send Feedback...
Page 578 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved rd_incr_ incr_ override overr RW 0x0 System Interconnect Altera Corporation Send Feedback...
Page 579 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. System Interconnect Altera Corporation Send Feedback...
Page 580 Bit Fields Reserved Reserved RW 0x0 write_qos Fields Name Description Access Reset QoS (Quality of Service) value for the write channel. A higher value has a higher priority. System Interconnect Altera Corporation Send Feedback...
Page 581 Reserved Reserved RW 0x0 fn_mod Fields Name Description Access Reset Value Description Multiple outstanding write transactions Only a single outstanding write transaction Value Description Multiple outstanding read transactions Only a single outstanding read transaction System Interconnect Altera Corporation Send Feedback...
Page 582: Document Revision History
Maintenance release November 2012 Minor updates. June 2012 • Added interconnect connectivity matrix. • Rearranged functional description sections. • Simplified address remapping section. • Added address map and register definitions section. January 2012 Initial release. System Interconnect Altera Corporation Send Feedback...
Page 583: Features Of The Hps-Fpga Bridges
FPGA Bridge Supports the AMBA AXI3 interface protocol 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos © are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants...
Page 584 FPGA bridges expose an AXI master interface that you can connect to AXI or Avalon-MM slave interfaces in the FPGA fabric. Related Information AXI Bridges on page 27-7 Information about configuring the AXI bridges HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 585: Hps-Fpga Bridges Block Diagram And System Integration
Access to the GPV registers of all three bridges is provided through the lightweight HPS-to-FPGA bridge. Related Information • Clocks and Resets on page 8-51 Functional Description of the System Interconnect • Detailed information about connectivity, such as which masters have access to each bridge HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 586: Functional Description Of The Hps-Fpga Bridges
Note: It is critical to provide the correct clock to support access to the GPV, as described in l4_mp_clk "GPV Clocks". The bridge slave data width is user-configurable at the time you instantiate the HPS component in your (19) system. HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 587 AWVALID 1 bit Output Write address channel ready AWREADY 5 bits Input User sideband signals AWUSER Table 8-4: FPGA-to-HPS Bridge Slave Write Data Channel Signals Signal Width Direction Description 8 bits Input Write ID HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 588 Lock type—Valid values are 00 (normal access) and ARLOCK 01 (exclusive access) 4 bits Input Cache policy type ARCACHE 3 bits Input Protection type ARPROT 1 bit Input Read address channel valid ARVALID 1 bit Output Read address channel ready ARREADY HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 589 8-11 Peripheral ID3 Register periph_id_3 on page 0x1FEC 8-11 Component ID0 Register comp_id_0 on page 8- 0x1FF0 Component ID1 Register comp_id_1 on page 8- 0x1FF4 0xF0 Component ID2 Register comp_id_2 on page 8- 0x1FF8 HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 590 8-9 Peripheral ID0 periph_id_1 on page 8-10 Peripheral ID1 periph_id_2 on page 8-11 Peripheral ID2 periph_id_3 on page 8-11 Peripheral ID3 comp_id_0 on page 8-12 Component ID0 comp_id_1 on page 8-13 Component ID1 HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 591 Bit Fields Reserved Reserved periph_id_4 RO 0x4 periph_id_4 Fields Name Description Access Reset JEP106 continuation code periph_id_4 periph_id_0 Peripheral ID0 Module Instance Base Address Register Address fpga2hpsregs 0xFF600000 0xFF601FE0 Offset: 0x1FE0 Access: HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 592 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved jep3to0_pn11to8 RO 0xB3 HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 593 Bit Fields Reserved Reserved rev_jepcode_jep6to4 RO 0x6B periph_id_2 Fields Name Description Access Reset Revision, JEP106 code flag, JEP106[6:4] rev_jepcode_jep6to4 0x6B periph_id_3 Peripheral ID3 Module Instance Base Address Register Address fpga2hpsregs 0xFF600000 0xFF601FEC Offset: 0x1FEC Access: HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 594 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved preamble RO 0xD HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 595 Bit Fields Reserved Reserved genipcompcls_preamble RO 0xF0 comp_id_1 Fields Name Description Access Reset Generic IP component class, Preamble genipcompcls_preamble 0xF0 comp_id_2 Component ID2 Module Instance Base Address Register Address fpga2hpsregs 0xFF600000 0xFF601FF8 Offset: 0x1FF8 Access: HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 596 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved preamble RO 0xB1 HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 597 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved bypass_ merge RW 0x0 HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 598 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 fn_mod Fields Name Description Access Reset Value Description Multiple outstanding write transactions Only a single outstanding write transaction HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 599 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved bypass_ merge RW 0x0 HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 600 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 fn_mod Fields Name Description Access Reset Value Description Multiple outstanding write transactions Only a single outstanding write transaction HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 601: Functional Description Of The Hps-To-Fpga Bridge
16 transactions 16 transactions Write acceptance 16 transactions 16 transactions Total acceptance 32 transactions 32 transactions The bridge master data width is user-configurable at the time you instantiate the HPS component in your (20) system. HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 602 8-24 Peripheral ID3 Register periph_id_3 on page 0x1FEC 8-24 Component ID0 Register comp_id_0 on page 8- 0x1FF0 Component ID1 Register comp_id_1 on page 8- 0x1FF4 0xF0 Component ID2 Register comp_id_2 on page 8- 0x1FF8 HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 603 8-22 Peripheral ID0 periph_id_1 on page 8-23 Peripheral ID1 periph_id_2 on page 8-24 Peripheral ID2 periph_id_3 on page 8-24 Peripheral ID3 comp_id_0 on page 8-25 Component ID0 comp_id_1 on page 8-26 Component ID1 HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 604 Bit Fields Reserved Reserved periph_id_4 RO 0x4 periph_id_4 Fields Name Description Access Reset JEP106 continuation code periph_id_4 periph_id_0 Peripheral ID0 Module Instance Base Address Register Address hps2fpgaregs 0xFF500000 0xFF501FE0 Offset: 0x1FE0 Access: HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 605 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved jep3to0_pn11to8 RO 0xB3 HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 606 Bit Fields Reserved Reserved rev_jepcode_jep6to4 RO 0x6B periph_id_2 Fields Name Description Access Reset Revision, JEP106 code flag, JEP106[6:4] rev_jepcode_jep6to4 0x6B periph_id_3 Peripheral ID3 Module Instance Base Address Register Address hps2fpgaregs 0xFF500000 0xFF501FEC Offset: 0x1FEC Access: HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 607 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved preamble RO 0xD HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 608 Bit Fields Reserved Reserved genipcompcls_preamble RO 0xF0 comp_id_1 Fields Name Description Access Reset Generic IP component class, Preamble genipcompcls_preamble 0xF0 comp_id_2 Component ID2 Module Instance Base Address Register Address hps2fpgaregs 0xFF500000 0xFF501FF8 Offset: 0x1FF8 Access: HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 609 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved preamble RO 0xB1 HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 610 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved bypass_ merge RW 0x0 HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 611 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 fn_mod Fields Name Description Access Reset Value Description Multiple outstanding write transactions Only a single outstanding write transaction HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 612 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved bypass_ merge RW 0x0 HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 613 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved RW 0x0 fn_mod Fields Name Description Access Reset Value Description Multiple outstanding write transactions Only a single outstanding write transaction HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 614: Functional Description Of The Lightweight Hps-To-Fpga Bridge
32 transactions The lightweight HPS-to-FPGA bridge has three master interfaces. The master interface connected to the FPGA fabric provides a lightweight interface from the HPS to custom logic in the FPGA fabric. The two HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 615 2 bits Output Burst type AWBURST 2 bits Output Lock type—Valid values are 00 (normal access) and AWLOCK 01 (exclusive access) 4 bits Output Cache policy type AWCACHE 3 bits Output Protection type AWPROT HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 616 Width Direction Description 12 bits Output Read address ID ARID 21 bits Output Read address ARADDR 4 bits Output Burst length ARLEN 3 bits Output Burst size ARSIZE 2 bits Output Burst type ARBURST HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 617 Peripheral ID4 Register periph_id_4 on page 0x1FD0 8-37 Peripheral ID0 Register periph_id_0 on page 0x1FE0 8-38 Peripheral ID1 Register periph_id_1 on page 0x1FE4 0xB3 8-38 Peripheral ID2 Register periph_id_2 on page 0x1FE8 0x6B 8-39 HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 618 Register Offset Width Acces Reset Value Description Bus Matrix Issuing Functionality fn_mod_bm_iss on page 0x5008 Modification Register 8-48 Write Tidemark wr_tidemark on page 0x5040 8-49 Issuing Functionality Modification fn_mod on page 8-49 0x5108 Register HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 619 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 620 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved pn7to0 RO 0x1 periph_id_0 Fields Name Description Access Reset Part Number [7:0] pn7to0 periph_id_1 Peripheral ID1 HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 621 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 622 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved rev_and cust_mod_num RO 0x0 RO 0x0 periph_id_3 Fields Name Description Access Reset Revision rev_and Customer Model Number cust_mod_num HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 623 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 624 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved preamble RO 0x5 comp_id_2 Fields Name Description Access Reset Preamble preamble comp_id_3 Component ID3 HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 625 Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. ahb_cntl on page 8-44 Sets the block issuing capability to one outstanding transaction. fn_mod_bm_iss Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 626 Value Description Multiple outstanding read transactions Only a single outstanding read transaction ahb_cntl Sets the block issuing capability to one outstanding transaction. Module Instance Base Address Register Address lwhps2fpgaregs 0xFF400000 0xFF402044 Offset: 0x2044 Access: HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 627 0x1000 fn_mod_bm_iss on page 8-46 Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. ahb_cntl on page 8-46 Sets the block issuing capability to one outstanding transaction. HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 628 Only a single outstanding write transaction Value Description Multiple outstanding read transactions Only a single outstanding read transaction ahb_cntl Sets the block issuing capability to one outstanding transaction. Module Instance Base Address Register Address lwhps2fpgaregs 0xFF400000 0xFF403044 HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 629 Registers associated with the 32-bit AXI master interface. This master provides access to slaves in the FPGA. Offset: 0x3000 fn_mod_bm_iss on page 8-48 Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 630 Reserved Reserved RW 0x0 fn_mod_bm_iss Fields Name Description Access Reset Value Description Multiple outstanding write transactions Only a single outstanding write transaction Value Description Multiple outstanding read transactions Only a single outstanding read transaction HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 631 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 632 Sets the block issuing capability to multiple or single outstanding transactions. fn_mod Sets the block issuing capability to multiple or single outstanding transactions. Module Instance Base Address Register Address lwhps2fpgaregs 0xFF400000 0xFF445108 Offset: 0x45108 Access: HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 633: Clocks And Resets
The master interface of the bridge in the HPS logic operates in the clock domain. The slave l3_main_clk interface exposed to the FPGA fabric operates in the clock domain provided by the user f2h_axi_clk HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 634 After the Cortex-A9 MPCore CPU boots, it can deassert the reset signal by clearing the appropriate bits in the reset manager's corresponding reset register. For details about reset registers, refer to "Module Reset Signals". Related Information Modules Requiring Software Deassert on page 3-9 Reset register names HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 635: Data Width Sizing
• FPGA Slaves Accessed via Lightweight HPS-to-FPGA AXI Bridge Related Information • FPGA2HPS AXI Bridge Module Address Map on page 8-7 HPS2FPGA AXI Bridge Module Address Map • on page 8-20 LWHPS2FPGA AXI Bridge Module Address Map • on page 8-35 HPS-FPGA Bridges Altera Corporation Send Feedback...
Page 636: Document Revision History
Reference Manual. HPS Peripheral Region Address Map • on page 1-17 Lists the base addresses of all modules Cyclone V Address Map and Register Definitions • Web-based address map and register definitions Document Revision History Table 8-16: Document Revision History...
Page 637: Features Of The Cortex-A9 Mpu Subsystem
L2-310 Level 2 Cache Controller 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos © are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants...
Page 638: Cortex-A9 Mpu Subsystem Block Diagram And System Integration
L2 cache can access either the system interconnect or the SDRAM. Figure 9-1: Cortex-A9 MPU Subsystem with Interconnect Block Diagram System MPU Subsystem Interconnect ARM Cortex-A9 MPCore Interrupts CPU0 CPU1 Debug Infrastructure ACP ID Mapper L2 Cache SDRAM Controller Subsystem Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 639: Cortex-A9 Mpu Subsystem Internals
Snoop Control Unit 512 KB L2 Cache ACP ID Mapper Debugging Modules CoreSight Multicore Debug and Trace Cross Triggering Event Trace CPU1 Performance Monitor CPU0 Performance Monitor CPU1 Program Trace CPU0 Program Trace Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 640: Cortex-A9 Mpcore
• Private interval timer for each processor core • Private watchdog timer for each processor core • Global timer • Interrupt controller Each transaction originating from the Altera Cortex-A9 MPU subsystem can be flagged as secure or non- secure. Related Information Cortex-A9 MPU Subsystem Register Implementation...
Page 641: Implementation Details
Implementation Details 2016.10.28 Implementation Details Table 9-2: Cortex-A9 MPCore Processor Configuration This table shows the parameter settings for the Altera Cortex-A9 MPCore. Feature Options Cortex-A9 processors 1 or 2 Instruction cache size per Cortex-A9 processor 32 KB Data cache size per Cortex-A9 processor...
Page 642: Cortex-A9 Processor
• 38% faster than the original Thumb instruction set • The Thumb instruction set—supported for legacy applications • Each processor core in the Altera HPS includes an MMU to support the memory management require‐ ments of common modern operating systems.
Page 643: Interactive Debugging Features
• A valid bit • TrustZone memory protection for the cache memory, with an NS (non-secure) state bit • A translation table base (TTB) address • An Address Space Identifier (ASID) value Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 644: Floating Point Unit
The NEON multimedia processing engine (MPE) provides hardware acceleration for media and signal processing applications. Each CPU includes an ARM NEON MPE that supports SIMD processing. Single Instruction, Multiple Data (SIMD) Processing Single Instruction Multiple Data Source Register Source Register Destination Register Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 645: Memory Management Unit
Two-way associative TLB Features The main TLB has the following features: • Lockable entries using the lock-by-entry model • Supports hardware page table walks to perform look-ups in the L1 data cache Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 646 Note: Alternatively, the boot region can be mapped to the 64 KB on-chip RAM. Related Information • Address Remapping on page 7-11 For more information about address remapping • System Interconnect on page 7-1 Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 647 However, you achieve this extended range at the expense of the FPGA peripheral address span. Depending on the address filter settings in the L2 cache, the top of the SDRAM region can range from 0xBFFFFFFF 0xFBFFFFFF Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 648: Performance Monitoring Unit
0xFC000000 . The HPS peripherals region is always allocated to the HPS dedicated peripherals for the 0xFFFFFFFF Altera Cortex-A9 MPU subsystem. Performance Monitoring Unit Each Cortex-A9 processor has a Performance Monitoring Unit (PMU). The PMU supports 58 events to gather statistics on the operation of the processor and memory system. Six counters in the PMU accumulate the events in real time.
Page 649: Generic Interrupt Controller
, running at ¼ the rate of mpu_periph_clk mpu_clk Related Information GIC Interrupt Map for the Cyclone V SoC HPS • on page 9-13 ARM Infocenter • For more information about the PL390 GIC, refer to the Interrupt Controller chapter of the Cortex-A9 MPCore Technical Reference Manual, available on the ARM Infocenter website.
Page 650 9-14 GIC Interrupt Map for the Cyclone V SoC HPS 2016.10.28 Source Block Interrupt Name Combined Interrupts Triggering Interrupt Number CortexA9_0 — Edge cpu0_parityfail_TLB CortexA9_0 — Edge cpu0_parityfail_D_Outer CortexA9_0 — Edge cpu0_parityfail_D_Tag CortexA9_0 — Edge cpu0_parityfail_D_Data CortexA9_0 — Level...
Page 651 9-15 GIC Interrupt Map for the Cyclone V SoC HPS 2016.10.28 Source Block Interrupt Name Combined Interrupts Triggering Interrupt Number CortexA9_1 — Level cpu1_deflags1 CortexA9_1 — Level cpu1_deflags2 CortexA9_1 — Level cpu1_deflags3 CortexA9_1 — Level cpu1_deflags4 CortexA9_1 — Level...
Page 652 9-16 GIC Interrupt Map for the Cyclone V SoC HPS 2016.10.28 Source Block Interrupt Name Combined Interrupts Triggering Interrupt Number FPGA — Level or FPGA_IRQ3 Edge FPGA — Level or FPGA_IRQ4 Edge FPGA — Level or FPGA_IRQ5 Edge FPGA —...
Page 653 9-17 GIC Interrupt Map for the Cyclone V SoC HPS 2016.10.28 Source Block Interrupt Name Combined Interrupts Triggering Interrupt Number FPGA — Level or FPGA_IRQ17 Edge FPGA — Level or FPGA_IRQ18 Edge FPGA — Level or FPGA_IRQ19 Edge FPGA —...
Page 654 9-18 GIC Interrupt Map for the Cyclone V SoC HPS 2016.10.28 Source Block Interrupt Name Combined Interrupts Triggering Interrupt Number FPGA — Level or FPGA_IRQ31 Edge FPGA — Level or FPGA_IRQ32 Edge FPGA — Level or FPGA_IRQ33 Edge FPGA —...
Page 655 9-19 GIC Interrupt Map for the Cyclone V SoC HPS 2016.10.28 Source Block Interrupt Name Combined Interrupts Triggering Interrupt Number FPGA — Level or FPGA_IRQ45 Edge FPGA — Level or FPGA_IRQ46 Edge FPGA — Level or FPGA_IRQ47 Edge FPGA —...
Page 656 9-20 GIC Interrupt Map for the Cyclone V SoC HPS 2016.10.28 Source Block Interrupt Name Combined Interrupts Triggering Interrupt Number FPGA — Level or FPGA_IRQ59 Edge FPGA — Level or FPGA_IRQ60 Edge FPGA — Level or FPGA_IRQ61 Edge FPGA —...
Page 657 9-21 GIC Interrupt Map for the Cyclone V SoC HPS 2016.10.28 Source Block Interrupt Name Combined Interrupts Triggering Interrupt Number EMAC0 — Level emac0_rx_ecc_corrected_IRQ EMAC0 — Level emac0_rx_ecc_uncorrected_ EMAC1 This interrupt combines: Level emac1_IRQ sbd_ intr_o lpi_intr_o EMAC1 —...
Page 658 9-22 GIC Interrupt Map for the Cyclone V SoC HPS 2016.10.28 Source Block Interrupt Name Combined Interrupts Triggering Interrupt Number SDMMC — Level sdmmc_IRQ SDMMC — Level sdmmc_porta_ecc_corrected_ SDMMC — Level sdmmc_porta_ecc_ uncorrected_IRQ SDMMC — Level sdmmc_portb_ecc_corrected_ SDMMC —...
Page 659 9-23 GIC Interrupt Map for the Cyclone V SoC HPS 2016.10.28 Source Block Interrupt Name Combined Interrupts Triggering Interrupt Number SPI2 This interrupt combines: Level spi2_IRQ ssi_ txe_intr ssi_txo_intr ssi_ rxf_intr ssi_rxo_intr ssi_ , and rxu_intr ssi_mst_intr SPI3 This interrupt combines:...
Page 660 9-24 GIC Interrupt Map for the Cyclone V SoC HPS 2016.10.28 Source Block Interrupt Name Combined Interrupts Triggering Interrupt Number I2C3 This interrupt combines: Level i2c3_IRQ ic_rx_ under_intr ic_rx_full_intr ic_tx_over_intr ic_tx_ empty_intr ic_rd_req_intr ic_tx_abrt_intr ic_rx_done_ intr ic_activity_intr stop_det_intr ic_start_det_...
Page 661: Global Timer
For more information about the global timer, refer to “About the Global Timer” in the Global timer, Private timers, and Watchdog registers chapter of the Cortex-A9 MPCore Technical Reference Manual, available on the ARM Infocenter website. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 662: Snoop Control Unit
S noop C o n t r ol Unit (SCU) Accelerator System Mastering Coherency Interconnect Level 2 (L2) Unified Cache Peripherals Port (ACP) Unidirectional Bidirectional Coherent Coherency Coherency Memory Related Information Accelerator Coherency Port on page 9-27 Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 663: Accelerator Coherency Port
Note: The entire 4 GB address space can be accessed coherently through the ACP through a 1 GB coherent window implemented through the ACP ID mapper. Note: Refer to the Cyclone V SoC device errata for details on ARM errata that directly affect the ACP. Related Information •...
Page 664 Coherent Memory, Snoop Control Unit, and Accelerator Coherency Port • on page 9-26 • Cyclone V SX, ST and SE SoC Device Errata AxUSER and AxCACHE Attributes ARUSER[0] and AWUSER[0] Bits The table below shows how the bit determines whether a request is shared or non-shared.
Page 665 CoreLink Level 2 Cache Controller L2C-310, Revision: r3p3 Technical Reference Manuel For more information about shareable attributes Configuring AxCACHE[3:0] Sideband Signals for Coherent Accesses The following list highlights how to correctly derive and apply the correct settings for coherent AxCACHE accesses. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 666 FPGA-to-HPS bridge that are upsized or downsized to the burst types above. For example, if the slave data width of the FPGA-to-HPS bridge is 32 bits, then bursts of eight beats by 32 bits are required to access the ACP efficiently. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 667: Acp Id Mapper
Note: Altera recommends that exclusive accesses bypass the ACP altogether, either through the 32-bit slave port of the SDRAM controller connected directly to the system interconnect or through the FPGA-to-SDRAM interface.
Page 668: Implementation Details
Debug Access Port (DAP) input ID. Related Information Cortex-A9 MPU Subsystem with System Interconnect on page 9-2 ID Intended Usage Table 9-7 summarizes the expected usage of the 3-bit output IDs, and their settings at reset. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 669 ACP ID mapper with an input ID that matches an already-in-progress transaction is mapped to the same output ID. Once all transactions on an ID mapping have completed, that output ID is released and can be used again for other input IDs. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 670 DMA Controller 4'b1000 sets the values to 4'b0101 (23) Values are in binary. The letter denotes variable ID bits that each master passes with each transaction. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 671 1000 0000 0100 1000 0000 0100 1000 0000 0000 1000 0000 0000 1000 0000 0000 (23) Values are in binary. The letter denotes variable ID bits that each master passes with each transaction. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 672 2-bit user-configured address page decode information. The page decoder uses the values shown in Table 9-9. (23) Values are in binary. The letter denotes variable ID bits that each master passes with each transaction. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 673: Acp Id Mapper Address Map And Register Definitions
Register for Fixed Virtual ID 4 Write AXI Master Mapping vid4wr on page 9-43 0x14 Register for Fixed Virtual ID 4 Read AXI Master Mapping vid5rd on page 9-44 0x18 Register for Fixed Virtual ID 5 Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 674 Read AXI Master Mapping Status dynrd_s on page 9-59 0x58 Register for Dynamic Virtual ID Remap Write AXI Master Mapping Status dynwr_s on page 9-60 0x5C Register for Dynamic Virtual ID Remap Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 675 This value is propagated to SCU as ARUSERS. user vid2wr The Write AXI Master Mapping Register contains the USER, ADDR page, and ID signals mapping values for particular transaction with 12-bit ID which locks the fixed 3-bit virtual ID. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 676 The Read AXI Master Mapping Register contains the USER, ADDR page, and ID signals mapping values for particular transaction with 12-bit ID which locks the fixed 3-bit virtual ID. Module Instance Base Address Register Address acpidmap 0xFF707000 0xFF707008 Offset: Access: Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 677 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 678 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 679 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 680 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 681 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 682 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 683 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 684 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 685 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved page Reserved user Reserved RW 0x0 RW 0x0 Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 686 The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit ID to use. 13:12 ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory page region. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 687 ID N, where N is the 3-bit ID to use. 13:12 AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB page memory region. This value is propagated to SCU as AWUSERS. user Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 688 The Write AXI Master Mapping Status Register contains the configured USER, ADDR page, and ID signals mapping values for particular transaction with 12-bit ID which locks the fixed 3-bit virtual ID. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 689 The Read AXI Master Mapping Status Register contains the configured USER, ADDR page, and ID signals mapping values for particular transaction with 12-bit ID which locks the fixed 3-bit virtual ID. Module Instance Base Address Register Address acpidmap 0xFF707000 0xFF707040 Offset: 0x40 Access: Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 690 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 691 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 692 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 693 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 694 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 695 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 696 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved page Reserved user Reserved RO 0x0 RO 0x0 Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 697: L2 Cache
• Write allocate • Read and write allocate • Single event upset (SEU) protection • Parity on Tag RAM • ECC on L2 Data RAM • Two slave ports mastered by the SCU Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 698 Tag RAM setup latency Data RAM write latency Data RAM read latency Data RAM setup latency Parity logic Parity logic enabled Lockdown by master Lockdown by master enabled Lockdown by line Lockdown by line enabled Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 699 Subsequently results in a hit or miss. Prefetch hint allocated into the L2 cache. EPFALLOC Prefetch hint hits in the L2 cache. EPFHIT Prefetch hint received by slave port S0. EPFRCVDS0 Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 700 RAM that are 64 bits wide (8 bytes, or one-quarter of the cache line length). The ECC logic does not perform a read-modify-write when calculating the ECC bits. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 701 If a parity error occurs on tag or data RAM during AXI write transactions, a SLVERR response is reported back through a SLVERRINTR interrupt signal. For Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 702 Data write lookup to the L2 cache. Subsequently DWREQ results in a hit or miss. Data write lookup to the L2 cache with DWTREQ write-through attribute. Subsequently results in a hit or miss. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 703 HPS-to-FPGA bridge and how much is allocated to SDRAM, depending on the configuration of the memory management unit. Related Information Cortex-A9 MPU Subsystem with System Interconnect • on page 9-2 Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 704: Cpu Prefetch
Table 9-13: Waypoints Supported by the PTM Type Additional Waypoint Information Indirect branches Target address and condition code Direct branches Condition code Instruction barrier instructions — Exceptions Location where the exception occurred Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 705: Event Trace
Related Information CoreSight Debug and Trace on page 10-1 For detailed information about cross-triggering and about debugging hardware in the MPU, refer to the CoreSight Debug and Trace chapter. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 706: Clocks
Related Information ARM Infocenter For detailed definitions of the registers for the Altera Cortex-A9 MPU subsystem, refer to the Cortex-A9 MPCore Technical Reference Manual, Revision r3p0 and the CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual, Revision r3p3, available on the ARM Infocenter website.
Page 707: Cortex-A9 Mpu Subsystem Address Map
Note: Any access to this region causes a SLVERR abort exception. This address space is Interrupt Distrib‐ 0xFFFED000 0xFFFEDFFF allocated for the utor interrupt distributor registers. This address space is Reserved 0xFFFEE000 0xFFFEEFFF reserved. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 708: L2 Cache Controller Address Map
This address space is Reserved 0xFFFEF800 0xFFFEF8FF reserved. This address space is Cache Lockdown 0xFFFEF900 0xFFFEF9FF allocated for cache lockdown registers. This address space is Reserved 0xFFFEFA00 0xFFFEFBFF reserved. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 709: Document Revision History
• Added "L2 Cache Parity" subsection in "L2 Cache" section May 2015 2015.05.04 Clarified EMAC0 and EMAC1 ACP Mapper IDs in the "HPS Peripheral Master Input IDs" table in the "HPS Peripheral Master Input IDs" section. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 710 December 2013 Correct SDRAM region address in ARM Cortex-A9 MPCoreAddress November 2012 Minor updates. May 2012 • Add description of the ACP ID mapper • Consolidate redundant information January 2012 Initial release. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 711 Program Trace Macrocell on page 10-11 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos © are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants...
Page 712: Features Of Coresight Debug And Trace
• CoreSight System Trace Macrocell Technical Reference Manual (ARM DDI 0444A) • System Trace Macrocell Programmers' Model Architecture Specification (ARM IHI 0054) • CoreSight Trace Memory Controller Technical Reference Manual (ARM DDI 0461B) CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 713: Coresight Debug And Trace Block Diagram And System Integration
I[7:4] I[1:0] Debug O[5:4] O[7:6] FPGA- csCTM Triggers to/from FPGA MPU Debug Subsystem Debug APB CTM 1 MPU Debug Timestamp Configuration Generator CTI-0 CTI-1 PTM-0 ATB PTM-1 ATB PTM-0 A9-0 A9-1 PTM-1 CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 714: Functional Description Of Coresight Debug And Trace
• on page 10-3 Shows CoreSight components connected to the debug APB Cyclone V Device Handbook Volume 1: Device Interfaces and Integration • For more information about boundary scan tests, refer to the "JTAG Boundary-Scan Testing in Cyclone V Devices" chapter.
Page 715: Trace Funnel
The Trace Funnel output is sent to the ETF. The ETF is used as an elastic buffer between trace generators (STM, PTM) and trace destinations. The ETF stores up to 32 KB of trace data in the on-chip trace RAM. CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 716: Amba Trace Bus Replicator
The ECT system provides a mechanism for the components listed in "Features of the CoreSight Debug and Trace" to trigger each other. The ECT consists of the following modules: • Cross Trigger Interface (CTI) • Cross Trigger Matrix (CTM) CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 717 Channel 3 Channel Interface Trigger Interface Related Information • Cross Trigger Interface on page 10-8 • Features of CoreSight Debug and Trace on page 10-2 Cross Trigger Matrix • on page 10-8 CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 718 The two CTMs are connected together, allowing triggers to be transmitted between the MPU debug subsystem, the debug system, and the FPGA fabric. Each CTM has four ports and each port has four channels. Each CTM port can be connected to a CTI or another CTM. CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 719 10-9 Cross Trigger Matrix 2016.10.28 Figure 10-4: CTM Channel Structure The following figure shows the structure of a CTM channel. Paths inside the CTM are purely combinato‐ rial. Channel 0 CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 720 Channel 0 Channel 1 Trigger Trigger Channel 2 Interface Interface Channel 3 Channel Interface Trigger Interface Related Information ARM Infocenter Refer to the CoreSight Components Technical Reference Manual on the ARM Infocenter website. CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 721: Program Trace Macrocell
32-bit system APB port read data bus h2f_dbg_apb_PRDATA[32] Ready signal to system APB port h2f_dbg_apb_PREADY Select signal from system APB port h2f_dbg_apb_PSEL Error signal to system APB port h2f_dbg_apb_PSLVERR 32-bit system APB port write data bus h2f_dbg_apb_PWDATA[32] CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 722 ACK signal from FPGA h2f_cti_trig_out_ack[8] Clock input from FPGA h2f_cti_clk Clock enable driven by FPGA h2f_cti_fpga_clk_en Signal from FPGA h2f_cti_asicctl[8] Related Information ARM Infocenter For more information about the cross-trigger interface CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 723 Note: When the FPGA is powered down or not configured, the TPIU sends the lower 8-bits trace data to I/Os. Clock from the FPGA used to capture trace data. h2f_tpiu_clock_in Clock output from TPIU h2f_tpiu_clock CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 724: Debug Clocks
Note: There are two fabric. It is asynchronous to Note: There are two signal names. . When through the JTAG clock soures. DAPCLK interface, this clock is the same of the JTAG interface. CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 725: Debug Resets
Use this signal to reset the DAP AHB-Lite master port. Reset manager Resets system APB slave port of PRESETSYSn sys_dbg_rst_n DAP. Reset manager CTM reset signal. It resets all nCTMRESET dbg_rst_n signals clocked by CTMCLK CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 726: Coresight Debug And Trace Programming Model
For more information about the CoreSight port names, refer to the CoreSight Technology System Design Guide. CoreSight Debug and Trace Programming Model This section describes programming model details specific to Altera’s implementation of the ARM CoreSight technology. The debug components can be configured to cause triggers when certain events occur. For example, soft logic in the FPGA fabric can signal an event which triggers an STM message injection into the trace stream.
Page 727: Stm Channels
The HPS address map allocates 48 MB of consecutive address space to the STM AXI slave port, divided in three 16 MB segments. Table 10-8: STM AXI Slave Port Address Allocation Segment Start Address End Address 0xFC000000 0xFCFFFFFF 0xFD000000 0xFDFFFFFF CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 728 FPGA through the FPGA-CTI. These event signals allow the FPGA fabric to send additional messages using the STM. Related Information HPS-FPGA Bridges • on page 8-1 ARM Infocenter • For more information, refer to "System Trace Macrocell" in the Programmers' Model Architecture Specification . CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 729: Cti Trigger Connections To Outside The Debug System
ACQCOMP FULL ACQCOMP FULL Table 10-12: csCTI Trigger Output Signals The following table lists the trigger output pin connections implemented for csCTI. Pin Number Signal Destination TRIGIN FLUSHIN HWEVENTS[3:2] HWEVENTS[1:0] TPIU TRIGIN CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 730: Configuring Embedded Cross-Trigger Connections
To access registers in any CoreSight component through the debugger, the register offsets must be added to the CoreSight component’s base address. That combined value must then be added to the address at which the ROM table is visible to the debugger (0x80000000). CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 731 Another soft logic signal in the FPGA connected to trigger input T2 in FPGA-CTI can be configured to trigger an STM message. csCTI output triggers 4 and 5 are wired to the STM CoreSight component in the CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 732: Coresight Debug And Trace Address Map And Register Definitions
This address space is allocated to the MPU L2 cache controller. For detailed information about the use of this address space, click here to access the ARM documentation for the L2C-310. Cyclone V Address Map and Register Definitions • Web-based address map and register definitions CoreSight Debug and Trace...
Page 733: System Trace Macrocell (Stm) Module Address Map
Trace Port Interface Unit. This is the address Trace Funnel 0xFF004000 0xFF004FFF space is allocated for the Trace Funnel. This address space is 0xFF005000 0xFF005FFF allocated for the System Trace Macrocell (STM). CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 734 CPU1 PMU. This address space is CTI0 0xFF118000 0xFF118FFF allocated for Cross- Trigger Interface 0 (CTI0). This address space is CTI1 0xFF119000 0xFF11BFFF allocated for Cross- Trigger Interface 1 (CTI1) CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 735: Mpu Address Map
Global Timer registers. This address space is Reserved 0xFFFEC300 0xFFFEC5FF reserved. This is the address Private Timers 0xFFFEC600 0xFFFEC6FF space is allocated for and Watchdog private timers and Timers watchdog timers. CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 736: Mpu L2 Cache Controller (L2C-310) Module Address Map
Counter Control Interrupt/Counter control registers. This address space is Reserved 0xFFFEF300 0xFFFEF6FF reserved. This is the address Cache 0xFFFEF700 0xFFFEF7FF space is allocated for Maintenance the cache maintenance Operations operation registers. CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 737: Document Revision History
Added address map and register definitions. February 2014 2014.02.28 Maintenance release. December 2013 2013.12.30 Maintenance release. November 2012 Minor updates. June 2012 Added functional description, programming model, and address map and register definition sections. CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 738 10-28 Document Revision History 2016.10.28 Date Version Changes January 2012 Initial release. CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 739: Features Of The Sdram Controller Subsystem
(24) The level of ECC support is package dependent. 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos © are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants...
Page 740: Sdram Controller Subsystem Block Diagram
8, and a command FIFO depth of 4. The MPU subsystem 64-bit AXI port and L3 interconnect 32-bit AXI port have asynchronous FIFO buffers with read and write data FIFO depth of 8, and command FIFO depth of 4. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 741: Sdram Controller Memory Options
1024 4096 (4 Gb) 1024 1024 1024 (1 Gb) 1024 DDR3 2048 (2 Gb) 1024 4096 (4 Gb) 1024 (25) For all memory types shown in this table, the DQ width is 8. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 742: Sdram Controller Subsystem Interfaces
System Interconnect on page 7-1 For all memory types shown in this table, the DQ width is 8. (25) S2 signifies a 2n prefetch size (26) (27) S4 signifies a 4n prefetch size SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 743: Csr Interface
The following table shows the number of ports needed to configure different bus protocols, based on type and data width. Table 11-3: FPGA-to-HPS SDRAM Port Utilization Bus Protocol Command Ports Read Data Ports Write Data Ports 32- or 64-bit AXI SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 744: Memory Controller Architecture
256-bit Avalon-MM write-only 32- or 64-bit Avalon-MM read-only 128-bit Avalon-MM read-only 256-bit Avalon-MM read-only Memory Controller Architecture The SDRAM controller consists of an MPFE, a single-port controller, and an interface to the CSRs. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 745: Multi-Port Front End
For each pending transaction, the command block calculates the next SDRAM burst needed to progress on that transaction. The command block schedules pending SDRAM burst commands based on the user-supplied configuration, available write data, and unallocated read data space. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 746: Single-Port Controller
Each SDRAM burst read or write is converted to the appropriate Altera PHY interface (AFI) command to open a bank on the correct row for the transac‐ tion (if required), execute the read or write command, and precharge the bank (if required).
Page 747 • Memory Controller Architecture on page 11-6 For more information, refer to the SDRAM Controller Block diagram. External Memory Interfaces in Cyclone V Devices • AFI Interface The AFI interface provides communication between the controller and the PHY. Related Information...
Page 748: Functional Description Of The Sdram Controller Subsystem
If multiple ports are of the same highest priority value, the port weight is applied to determine which port wins. Because the arbiter only allows SDRAM-sized bursts into the single-port memory controller, large transactions may SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 749 This 30-bit register uses 3 bits per port to configure the priority. The lowest priority is mppriority 0x0 and the highest priority is 0x7. The bits are mapped in ascending order with bits [2:0] assigned to command port 0 and bits [29:27] assigned to command port 9. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 750 20% of bandwidth is allocated to the Avalon-MM port. With these port settings, any FPGA transaction buffered by the MPFE for either slave port blocks the MPU and L3 masters from having their buffered SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 751: Mpfe Sdram Burst Scheduling
Because the mppriority registers can be updated in a single 32-bit transaction, Altera recommends mpweight_*_4 updating first to ensure that transactions that need to be serviced have the appropriate priority after the next update.
Page 752: Single-Port Controller Operation
Data reordering allows the write and read operations to occur in bursts, without bus turnaround timing delay or bank reassign‐ ment. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 753 24 and 40 bits are supported for operations with ECC enabled. The following table shows the type of SDRAM for each burst length. Table 11-6: SDRAM Burst Lengths Burst Length SDRAM LPDDR2, DDR2 DDR2, DDR3, LPDDR2 SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 754 Note: Double-bit errors do not generate read-modify-write commands. Instead, double-bit error address and count are reported through the registers, respectively. In addition, a erraddr dbecount double-bit error interrupt can be enabled through the register. dramintr SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 755 The following interleaving examples use 512 megabits (Mb) x 16 DDR3 chips and are documented as byte addresses. For RAMs with smaller address fields, the order of the fields stays the same but the widths may change. Non-interleaved RAM mapping is non-interleaved. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 756 (giving access to 16 total banks for multithreaded access to blocks of memory). Memory timing is degraded when switching between chips. Figure 11-6: Bank Interleave With Chip Select Interleave Address Decoding R ( 15 :0 ) B ( 2 :0) C ( 9:0 ) SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 757: Memory Protection
When this bit is clear, allow CPU reads during a default transaction. When this bit is set to 1, deny L3 reads during a default transaction. When this bit is clear, allow L3 reads during a default transaction. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 758 (28) of rules. If masters connected to a port do not have contiguous AxIDs, a port-based rule might be more efficient than an AxID-based rule, in terms of the number of rules needed. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 759 The following figure represents an overview of how the protection rules are applied. There is no priority among the 20 rules. All rules are always evaluated in parallel. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 760 Consequently, a master performing an exclusive read followed by a write, can write to memory only if the exclusive read was successful. Related Information ARM TrustZone For more information about TrustZone refer to the ARM web page. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 761 The port mask value, AxID Low, and AxID High, apply to all ports and all transfers within those ports. Each access request is evaluated against the memory protection table, and will fail unless there is a rule match allowing a transaction to complete successfully. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 762: Sdram Power Management
Power-down mode forces the SDRAM burst-scheduling bank-management logic to close all banks and issue the power down command. The SDRAM automatically reactivates when an active SDRAM command is received. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 763: Ddr Calibration
Clock Name Description Clock for PHY ddr_dq_clk Clock for MPFE, single-port controller, CSR access, and PHY ddr_dqs_clk Clock for PHY that provides up to 2 times frequency ddr_dq_clk ddr_2x_dqs_clk Clock for CSR interface l4_sp_clk SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 764: Resets
For more details about reset registers, refer to the Reset Manager. Port Mappings The memory interface controller has a set of command, read data, and write data ports that support AXI3, AXI4 and Avalon-MM. Tables are provided to identify port assignments and functions. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 765: Initialization
DRAM type, DRAM timing parameters and relative port priorities. It also has a small set of bits which depend on the FPGA fabric to configure ports between the memory controller and SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 766: Fpga-To-Sdram Protocol Details
Write data for a transaction writedata 4, 8, 16, 32 Byte enables for each write byte lane byteenable (29) The Avalon-MM protocol does not allow read and write transactions to be posted concurrently. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 767 32, 64, 128, or 256 Write data for a transaction writedata 4, 8, 16, 32 Byte enables for each write byte byteenable Indicates need for additional cycles to waitrequest complete a transaction Transaction burst length burstcount SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 768 Because the AXI protocol allows simultaneous read and write commands to be issued, two SDRAM control ports are required to form an AXI interface. Table 11-18: AXI Port Signals Name Bits Direction Channel Function Reset ARESETn SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 769 Width of the transfer size ARSIZE Read address Burst type ARBURST Read address Lock type signal which indicates if the ARLOCK access is exclusive; valid values are 0x0 (normal access) and 0x1 (exclusive access) SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 770: Sdram Controller Subsystem Programming Model
To configure the external memory interface components of the HPS, open the HPS interface by selecting the Arria V/Cyclone V Hard Processor System component in Qsys. Within the HPS interface, select the EMIF tab to open the EMIF parameter editor.
Page 771: Hps Memory Interface Simulation
<base name>.hps.fpga_interfaces.h2f_reset_inst.reset_assert(); // Delay // Deassert reset <base name>.hps.fpga_interfaces.h2f_reset_inst.reset_deassert(); Generating a Preloader Image for HPS with EMIF To generate a Preloader image for an HPS-based external memory interface, you must complete the following tasks: SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 772 Note: You must regenerate the hardware handoff files whenever the HPS configuration changes; for example, due to changes in Peripheral Pin Multiplexing or I/O standard for HPS pins. Related Information Altera SoC Embedded Design Suite User Guide For more information on how to create a preloader BSP file and image. SDRAM Controller Subsystem...
Page 773: Debugging Hps Sdram In The Preloader
1. When you create the file in the BSP Editor, select SEMIHOSTING in the spl.debug window. .bsp 2. Enable semihosting in the debugger, by typing at the command line set semihosting enabled true in the debugger. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 774: Enabling Simple Memory Test
BSP Editor, select HARDWARE_DIAGNOSTIC in the spl.debug .bsp window.. 2. The simple memory test assumes SDRAM with a memory size of 1 GB. If your board contains a different SDRAM memory size, open the file <design folder>\spl_bsp\uboot-socfpga\ SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 775: Enabling The Debug Report
1. After you have enabled the UART or semihosting, open the file <project directory>\hps_isw_ in a text editor. handoff\sequencer_defines.h 2. Locate the line and change it to #define RUNTIME_CAL_REPORT 0 #define RUNTIME_CAL_REPORT 1 SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 776 11-38 Analysis of Debug Report 2016.10.28 Figure 11-9: Semihosting Printout With Debug Support Enabled Analysis of Debug Report The following analysis will help you interpret the debug report. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 777 Note: The Write Deskew, Read Deskew, DM Deskew, and Read after Write results are reported in delay steps (nominally 25ps, in Arria V and Cyclone V devices), not in picoseconds. • DQS Enable calibration is reported as a VFIFO setting (in one clock period steps), a phase tap (in one- eighth clock period steps), and a delay chain step (in 25ps steps).
Page 778: Writing A Predefined Data Pattern To Sdram In The Preloader
(cnt = (0+i*num_address); cnt < ((i+1)*num_address) ; cnt = cnt++ ) { addr = base + cnt; /* pointer arith! */ sync (); read_data=*addr; printf("Address:%X Expected: %08X Read:%08X \n",addr, expected_data[i],read_data); if (expected_data[i] !=read_data) { puts("!!!!!!FAILED!!!!!!\n\n"); hang(); expected_data[i]=ROTATE_RIGHT(expected_data[i]); ====//End Of Code//===== SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 779: Sdram Controller Address Map And Register Definitions
DRAM Timings 3 Register dramtiming3 on page 0x500C 11-50 DRAM Timings 4 Register dramtiming4 on page 0x5010 11-50 Lower Power Timing Register lowpwrtiming on page 0x5014 11-51 ODT Control Register dramodt on page 11- 0x5018 SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 780 0x5090 Register 11-68 Memory Protection ID Register protruleid on page 0x5094 11-69 Memory Protection Rule Data protruledata on page 0x5098 Register 11-70 Memory Protection Rule Read- protrulerdwr on page 0x509C Write Register 11-71 SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 781 This register implements JEDEC standardized timing parameters. It should be programmed in clock cycles, for the value specified by the memory vendor. lowpwrtiming on page 11-51 This register controls the behavior of the low power logic in the controller. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 782 1. autopchen fpgaportrst on page 11-66 This register implements functionality to allow the CPU to control when the MPFE will enable the ports to the FPGA fabric. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 783 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 784 This should only be used for testing purposes. Enable the deliberate insertion of single bit errors in gensbe data written to memory. This should only be used for testing purposes. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 785 Bank interleaved with column rank (chip select) interleaving reserved Altera recommends programming addrorder to 0x0 or 0x2. Configures burst length as a static decimal value. membl Legal values are valid for JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, this should be programmed with 8 (binary "01000"),...
Page 786 RW 0x0 RW 0x0 dramtiming1 Fields Name Description Access Reset 31:24 The refresh cycle timing parameter. trfc 23:18 The four-activate window timing parameter. tfaw 17:14 The activate to activate, different banks timing trrd parameter. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 787 The write to read timing parameter. twtr 24:21 The write recovery timing. 20:17 The precharge to activate timing parameter. 16:13 The activate to read/write timing parameter. trcd 12:0 The refresh interval timing parameter. trefi SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 788 The read to precharge timing parameter. trtp dramtiming4 This register implements JEDEC standardized timing parameters. It should be programmed in clock cycles, for the value specified by the memory vendor. Module Instance Base Address Register Address 0xFFC20000 0xFFC25010 SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 789 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 790 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved cfg_read_odt_chip cfg_write_odt_chip RW 0x0 RW 0x0 SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 791 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved csbits bankbits rowbits colbits RW 0x0 RW 0x0 RW 0x0 RW 0x0 SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 792 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 793 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved corrd dbeer sbeer calfa calsucce RW 0x0 SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 794 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved intrc corrd dbema sbema intren ropma RW 0x0 SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 795 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved count RW 0x0 SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 796 Reports the number of double bit errors that have count occurred since the status register counters were last cleared. erraddr This register holds the address of the most recent ECC error. Module Instance Base Address Register Address 0xFFC20000 0xFFC25048 SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 797 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved corrdropcount RW 0x0 SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 798 This register instructs the controller to put the DRAM into a power down state. Note that some commands are only valid for certain memory types. Module Instance Base Address Register Address 0xFFC20000 0xFFC25054 Offset: 0x5054 SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 799 DRAMs, DDR3 DRAMs do not support deep power down. lowpwrack This register gives the status of the power down commands requested by the Low Power Control register. Module Instance Base Address Register Address 0xFFC20000 0xFFC25058 SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 800 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 801 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 802 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 803 Bit 6 L3 read Bit 5 FPGA-to-SDRAM port 5 Bit 4 FPGA-to-SDRAM port 4 Bit 3 FPGA-to-SDRAM port 3 Bit 2 FPGA-to-SDRAM port 2 Bit 1 FPGA-to-SDRAM port 1 Bit 0 FPGA-to-SDRAM port 0 SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 804 This register implements functionality to allow the CPU to control when the MPFE will enable the ports to the FPGA fabric. Module Instance Base Address Register Address 0xFFC20000 0xFFC25080 Offset: 0x5080 Access: SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 805 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 806 The default state of this register is to allow all access. Address values used for protection are only physical addresses. Module Instance Base Address Register Address 0xFFC20000 0xFFC25090 Offset: 0x5090 Access: SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 807 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 808 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved ruler portmask valid security esult rule RW 0x0 RW 0x0 SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 809 0x2 or 0x3 Rule applies to secure and non-secure transactions protrulerdwr This register is used to perform read and write operations to the internal protection table. Module Instance Base Address Register Address 0xFFC20000 0xFFC2509C Offset: 0x509C SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 810 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 811 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved priorityremap RW 0x0 SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 812 This register is used to configure the DRAM burst operation scheduling. mpweight_0_4 This register is used to configure the DRAM burst operation scheduling. Module Instance Base Address Register Address 0xFFC20000 0xFFC250B0 Offset: 0x50B0 Access: SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 813 This register is used to configure the DRAM burst operation scheduling. Module Instance Base Address Register Address 0xFFC20000 0xFFC250B4 Offset: 0x50B4 Access: Bit Fields sumofweights_13_0 staticweight_ 49_32 RW 0x0 RW 0x0 staticweight_49_32 RW 0x0 SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 814 This register is used as part of the deficit round robin implementation. It should be set to the sum of the weights for the ports mpweight_3_4 This register is used to configure the DRAM burst operation scheduling. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 815: Document Revision History
This register is used as part of the deficit round robin implementation. It should be set to the sum of the weights for the ports Document Revision History Date Version Changes October 2016 2016.10.28 Maintenance release May 2016 2016.05.03 Maintenance release SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 816 • Added Generating a Preloader Image for HPS with EMIF section. • Added Debugging HPS SDRAM in the Preloader section. • Enhanced Simulation section. November 2012 Added address map and register definitions section. January 2012 Initial release. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 817: On-Chip Ram
The entire RAM is either secure or non-secure. Security is enforced by the NIC-301 L3 interconnect. 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos ©...
Page 818: Functional Description Of The On-Chip Ram
On-Chip Memory Address Map and Register Definitions • on page 12-4 • System Manager on page 5-1 For more information about ECC, refer to the System Manager chapter of the Cyclone V Device Handbook. On-Chip Memory Altera Corporation Send Feedback...
Page 819: Boot Rom
NIC-301 L3 interconnect. All writes return an error response. Related Information Clock Manager • on page 2-1 • Booting and Configuration on page 30-1 Boot ROM Clocks Related Information Clock Manager on page 2-1 On-Chip Memory Altera Corporation Send Feedback...
Page 820: On-Chip Memory Address Map And Register Definitions
Table 12-2: Boot ROM Address Range Module Instance Start Address End Address bootROM 0xFFFD0000 0xFFFDFFFF Document Revision History Table 12-3: Document Revision History Date Version Changes October 2016 2016.10.28 Maintenance release May 2016 2016.05.03 Maintenance release On-Chip Memory Altera Corporation Send Feedback...
Page 821 December 2014 2014.12.15 Maintenance release June 2014 2014.06.30 Added address maps and register definitions February 2014 2014.02.28 Maintenance release December 2013 2013.12.30 Maintenance release November 2012 Added address map section January 2012 Initial release On-Chip Memory Altera Corporation Send Feedback...
Page 822: Nand Flash Controller Features
Supported Flash Devices for Cyclone V and Arria V SoC For more information, refer to the supported NAND flash devices section on this page. 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos ©...
Page 823: Nand Flash Controller Block Diagram And System Integration
• The DMA master interface provides accesses to and from the flash controller through the controller's built-in DMA. NAND Flash Controller Signal Descriptions The HPS I/O pins support a single x8 device. The following table lists the signals: NAND Flash Controller Altera Corporation Send Feedback...
Page 824: Functional Description Of The Nand Flash Controller
3. If the data returned by the memory device has an ONFI signature, the flash controller then reads the device parameter page. The flash controller stores the relevant device feature information in internal NAND Flash Controller Altera Corporation Send Feedback...
Page 825: Bootstrap Interface
Example Value for 512-Byte Page (30) noinit page512 noloadb0p0 When this register is set, the NAND flash controller expects the host to program the related device parameter (30) registers. For more information, refer to "Configuration by Host". NAND Flash Controller Altera Corporation Send Feedback...
Page 826: Configuration By Host
Each NAND page has a main area and a spare area. The main area is intended for data storage. The spare area is intended for ECC and maintenance data, such as wear leveling information. Each block consists of a group of pages. (31) All registers are in the group. config NAND Flash Controller Altera Corporation Send Feedback...
Page 827: Local Memory Buffer
Since the NAND places a 200 MHz limit on the clock, each of these four generated clocks are 50 MHz and called nand_clk NAND Flash Controller Altera Corporation Send Feedback...
Page 828: Resets
Indexed addressing uses registers in the nanddata region of the HPS memory map. The nanddata region consists of a control register and a variable-size register that allows direct access to flash memory, as detailed in the following table. NAND Flash Controller Altera Corporation Send Feedback...
Page 829: Command Mapping
The NAND flash controller supports the following flash controller-specific MAP commands: • MAP00 commands—boot-read or buffer read/write during read-modify-write operations • MAP01 commands—memory arrays read/write • MAP10 commands—NAND flash controller commands • MAP11 commands—low-level direct access NAND Flash Controller Altera Corporation Send Feedback...
Page 830 Because the NAND flash controller does not perform ECC correction during such an operation, Altera does not recommend this method in an MLC device. • In association with MAP11 commands, MAP00 commands provide a way for the host to directly access the device bypassing the hardware abstractions provided by NAND flash controller with MAP01 and MAP10 commands.
Page 831 • 128 pages per block: <M>=7 • 256 pages per block: <M>=8 • 384 pages per block: <M>=9 • 512 pages per block: <M>=9 MAP01 Usage Limitations Use the MAP01 command as follows: NAND Flash Controller Altera Corporation Send Feedback...
Page 832 • 32 pages per block: <M>=5 • 64 pages per block: <M>=6 • 128 pages per block: <M>=7 • 256 pages per block: <M>=8 • 384 pages per block: <M>=9 • 512 pages per block: <M>=9 NAND Flash Controller Altera Corporation Send Feedback...
Page 833 Sets copy destination address and initiates a copy of <PP> pages 0x20<PP> Sets up a pipeline read-ahead of <PP> pages 0x21<PP> Sets up a pipeline write of <PP> pages MAP10 Usage Limitations Use the MAP10 commands as follows: NAND Flash Controller Altera Corporation Send Feedback...
Page 834 The following table shows the format of a MAP11 command. This command is written to the Command register in the region. nanddata Address Bits Name Description 31:28 (reserved) Set to 0 27:26 Set to 3 CMD_MAP 25:2 (reserved) Set to 0 NAND Flash Controller Altera Corporation Send Feedback...
Page 835: Data Dma
DMA mode is enabled because the flash controller is operating in an extremely tightly-coupled, high-performance data transfer mode. On receipt of erroneous commands (MAP00, MAP01 or MAP11), the flash controller issues an interrupt to inform the host about the unsup_cmd violating command. NAND Flash Controller Altera Corporation Send Feedback...
Page 836 To initiate DMA with a multitransaction DMA command, you send four command-data pairs to the NAND flash controller through the Control and Data registers in the region, as shown in nanddata "Command-Data Pair Formats". Related Information Command-Data Pair Formats on page 13-16 NAND Flash Controller Altera Corporation Send Feedback...
Page 837 <M> depends on the number of pages per block in the device. For more information about <M>, see the (32) Note at the bottom of this table. (33) The buffer address in host memory, which must be aligned to 32 bits. NAND Flash Controller Altera Corporation Send Feedback...
Page 838 INT specifies the host interrupt to be generated at the end of the complete DMA transfer. For more (34) information about INT, see the Note at the bottom of this table. (35) Can be only 4, 16, 32, or 64 bytes. No other values are valid. NAND Flash Controller Altera Corporation Send Feedback...
Page 839 You can optionally send the 16-bit fields in the above table to the NAND flash controller as four separate bursts of length 1 in sequential order. Altera recommends this method. If you want the NAND flash controller DMA to perform cacheable accesses, you must configure the cache...
Page 840 The NAND flash controller does not introduce or interpret ECC check bits in spare area transfer mode, and acts as a pass-through for data transfer. Figure 13-3: Spare Area Transfer Mode for ECC Sector 3 ECC3 Flags NAND Flash Controller Altera Corporation Send Feedback...
Page 841 The host writes both the data sectors and the bad block markers. The flash controller depends on the host software to set up the bad block markers properly before writing the data. NAND Flash Controller Altera Corporation Send Feedback...
Page 842: Nand Flash Controller Programming Model
Note: If you write a configuration register and follow it up with a data operation that is dependent on the value of this configuration register, Altera recommends that you read the value of the register before performing the data operation. This read operation ensures that the posted write of the register is completed and takes effect before the data operation is issued to the NAND flash controller.
Page 843: Basic Flash Programming
NAND flash controller cannot identify it correctly. If you are using such a device, your software must use other means to ensure that the initialization registers are set up correctly. NAND Flash Controller Altera Corporation Send Feedback...
Page 844 • Initialize the register to the appropriate correction level. ecc_correction • Program the registers in the group if the spare_area_skip_bytes spare_area_marker config software needs to preserve the bad block marker. Related Information on page 13-18 NAND Flash Controller Altera Corporation Send Feedback...
Page 845 Altera recommends that the software reads back this register to ensure clearing an interrupt status. This recommendation applies also to an interrupt service routine. 3. Enable DMA if your application needs DMA mode. Enable DMA by setting the...
Page 846: Flash-Related Special Function Operations
Before data can be written to flash, an erase cycle must occur. The NAND flash memory controller supports single block and multi-plane erases. The controller decodes the block address from the indirect addressing shown in "MAP10 Command Format". Related Information MAP10 Command Format on page 13-11 NAND Flash Controller Altera Corporation Send Feedback...
Page 847 4. Write 0x11 to the register. Data When unlocking a range of blocks, the start block address must be less than the end block address. Otherwise, the NAND flash controller exhibits undetermined behavior. NAND Flash Controller Altera Corporation Send Feedback...
Page 848 Resulting NAND Flash Controller Mode 0x42 Main (39) 0x41 Spare 0x43 Main+spare 0x42 Main+spare (39) Default access mode (0x42) maps to either main (only) or main+spare mode, depending on the value of (39) transfer_spare_reg NAND Flash Controller Altera Corporation Send Feedback...
Page 849 Note: Because the data is modified within the page buffer of the flash device, the NAND flash controller ECC hardware is not used in RMW operations. Software must update the ECC during RMW operations. NAND Flash Controller Altera Corporation Send Feedback...
Page 850 ECC data, but does not check it during the copy operation. Note: Altera recommends that you use copy-back only if the ECC implemented in the flash controller is strong enough so that the next access can correct accumulated errors.
Page 851 The pipeline read-ahead function allows for a continuous reading of the flash memory. On receiving a pipeline read command, the flash controller immediately issues a load command to the device. While data is read out with MAP01 commands in a consecutive or multi-plane address pattern, the flash controller NAND Flash Controller Altera Corporation Send Feedback...
Page 852 Pipeline Write-Ahead Function The pipeline write-ahead function allows for a continuous writing of the flash memory. While data is written with MAP01 commands in a consecutive or multi-plane address pattern, the NAND flash NAND Flash Controller Altera Corporation Send Feedback...
Page 853 An additional interrupt is generated when the last page program operation completes in program_comp the case of a pipeline write command. NAND Flash Controller Altera Corporation Send Feedback...
Page 854: Nand Flash Controller Address Map And Register Definitions
The base addresses of all modules are also listed in the Introduction to the Hard Processor System chapter. • Cyclone V Address Map and Register Definitions Web-based address map and register definitions NAND Controller Module Data (AXI Slave) Address Map This address space is allocated for indexed addressing by the NAND flash controller.
Page 855: Nand Flash Controller Module Registers (Axi Slave) Address Map
13-49 cache_write_enable 0xA0 page 13-50 cache_read_enable 0xB0 page 13-50 prefetch_mode on page 0xC0 13-51 chip_enable_dont_care 0xD0 on page 13-52 ecc_enable on page 0xE0 13-53 global_int_enable 0xF0 page 13-53 twhr2_and_we_2_re 0x100 0x1432 page 13-54 NAND Flash Controller Altera Corporation Send Feedback...
Page 856 0x1E0 13-67 rdwr_en_lo_cnt 0x1F0 0x12 page 13-68 rdwr_en_hi_cnt 0x200 page 13-69 max_rd_delay on page 0x210 13-70 cs_setup_cnt on page 0x220 13-71 spare_area_skip_bytes 0x230 on page 13-71 spare_area_marker 0x240 0xFFFF page 13-72 NAND Flash Controller Altera Corporation Send Feedback...
Page 857 0x330 page 13-81 device_param_2 0x340 page 13-82 logical_page_data_siz 0x350 on page 13-82 logical_page_spare_si 0x360 on page 13-83 revision on page 13- 0x370 onfi_device_features 0x380 on page 13-84 onfi_optional_command 0x390 on page 13-85 NAND Flash Controller Altera Corporation Send Feedback...
Page 858 13- 0x430 err_page_addr0 0x440 page 13-97 err_block_addr0 0x450 page 13-98 intr_status1 on page 0x460 13-98 intr_en1 on page 13- 0x470 0x2000 page_cnt1 on page 13- 0x480 err_page_addr1 0x490 page 13-102 NAND Flash Controller Altera Corporation Send Feedback...
Page 859: Dma Registers
Offset Width Acces Reset Value Description ECCCorInfo_b01 0x650 page 13-115 ECCCorInfo_b23 0x660 page 13-116 DMA registers Register Offset Width Acces Reset Value Description dma_enable on page 0x700 13-117 dma_intr on page 13- 0x720 NAND Flash Controller Altera Corporation Send Feedback...
Page 860 13-47 Interrupt or polling mode. Ready/Busy pin is enabled from device. multiplane_operation on page 13-48 Multiplane transfer mode. Pipelined read, copyback, erase and program commands are transfered in multiplane mode NAND Flash Controller Altera Corporation Send Feedback...
Page 861 13-62 Address restriction for multiplane commands ecc_correction on page 13-62 Correction capability required read_mode on page 13-63 The type of read sequence that the controller will follow for pipe read commands. NAND Flash Controller Altera Corporation Send Feedback...
Page 862 The number of cycles the controller waits before flagging a watchdog timeout interrupt. device_reset Device reset. Controller sends a RESET command to device. Controller resets bit after sending command to device Module Instance Base Address Register Address nandregs 0xFFB80000 0xFFB80000 Offset: Access: NAND Flash Controller Altera Corporation Send Feedback...
Page 863 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. NAND Flash Controller Altera Corporation Send Feedback...
Page 864 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved value RW 0x1F4 NAND Flash Controller Altera Corporation Send Feedback...
Page 865 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved value RW 0x1F4 NAND Flash Controller Altera Corporation Send Feedback...
Page 866 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved value RW 0x1F4 NAND Flash Controller Altera Corporation Send Feedback...
Page 867 In polling mode, sets the number of cycles Denali value 0x1F4 Flash Controller must wait before checking the status register. This register is only used when R/B pins are not available to NAND Flash Controller. NAND Flash Controller Altera Corporation Send Feedback...
Page 868 1. Polling mode.[/list] Sets Denali Flash Controller in interrupt pin or bank0 polling mode [list][*]1 - R/B pin enabled for bank 0. Interrupt pin mode. [*]0 - R/B pin disabled for bank 0. Polling mode.[/list] NAND Flash Controller Altera Corporation Send Feedback...
Page 869 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. NAND Flash Controller Altera Corporation Send Feedback...
Page 870 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved flag RW 0x0 NAND Flash Controller Altera Corporation Send Feedback...
Page 871 Description Access Reset [list][*]1 - Cache write supported [*]0 - Cache write flag not supported[/list] cache_read_enable Device supports cache read command sequence Module Instance Base Address Register Address nandregs 0xFFB80000 0xFFB800B0 Offset: 0xB0 NAND Flash Controller Altera Corporation Send Feedback...
Page 872 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved prefetch_burst_length Reserved prefetch RW 0x0 RW 0x1 NAND Flash Controller Altera Corporation Send Feedback...
Page 873 Fields Name Description Access Reset Controller can interleave commands between banks flag when this feature is enabled. [list][*]1 - Device in dont care mode [*]0 - Device cares for chip enable[/ list] NAND Flash Controller Altera Corporation Send Feedback...
Page 874 When disabled, controller does not compute check-bits. [list][*]1 - ECC Enabled [*]0 - ECC disabled[/list] global_int_enable Global Interrupt enable and Error/Timeout disable. Module Instance Base Address Register Address nandregs 0xFFB80000 0xFFB800F0 Offset: 0xF0 Access: NAND Flash Controller Altera Corporation Send Feedback...
Page 875 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. NAND Flash Controller Altera Corporation Send Feedback...
Page 876 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved tcwaw Reserved addr_2_data RW 0x14 RW 0x32 NAND Flash Controller Altera Corporation Send Feedback...
Page 877 Signifies the number of bus interface nand_mp_clk value 0x32 clocks that should be introduced between read enable going high to write enable going low. The number of clocks is the function of device parameter Trhw and controller clock frequency. NAND Flash Controller Altera Corporation Send Feedback...
Page 878 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. NAND Flash Controller Altera Corporation Send Feedback...
Page 879 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved value RW 0x0 NAND Flash Controller Altera Corporation Send Feedback...
Page 880 Controller will read Electronic Signature of devices value and populate this field. After reset, this field must be set to 0, indicating an 8-bit device. device_main_area_size Page main area size of device in bytes NAND Flash Controller Altera Corporation Send Feedback...
Page 881 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. NAND Flash Controller Altera Corporation Send Feedback...
Page 882 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved flag RW 0x0 NAND Flash Controller Altera Corporation Send Feedback...
Page 883 The last plane address cycles has proper values. This ensures multiplane address restrictions in the device. ecc_correction Correction capability required NAND Flash Controller Altera Corporation Send Feedback...
Page 884 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. NAND Flash Controller Altera Corporation Send Feedback...
Page 885 13-64 read_mode 2016.10.28 Bit Fields Reserved Reserved value RW 0x0 NAND Flash Controller Altera Corporation Send Feedback...
Page 886 CE0, Data, C00, Address, C05, Address, CE0, Data, .., C3F, C00, Address, C05, Address, CE0, Data, C00, Address, C05, Address, CE0, Data NAND Flash Controller Altera Corporation • [*]4'h9 - 4'h15 - Reserved. indicates that the previous sequence is repeated till the Send Feedback...
Page 887 • 4'h3 - This value informs the controller that the pipe write sequence to follow is of a 'N' Plane Program with the following sequence, C80, Address, Data, C11, C80, Address, Data, C10..NAND Flash Controller Altera Corporation Send Feedback...
Page 888 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved value RW 0x0 copyback_mode Fields Name Description Access Reset The values in the field should be as follows value NAND Flash Controller Altera Corporation Send Feedback...
Page 889 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. NAND Flash Controller Altera Corporation Send Feedback...
Page 890 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved value RW 0xC NAND Flash Controller Altera Corporation Send Feedback...
Page 891 Data should have been registered with nand_mp_clk and stable by the time max_rd_delay cycles has elapsed. A default value of zero will mean a value of nand_mp_clk multiple minus one. NAND Flash Controller Altera Corporation Send Feedback...
Page 892 ONFI Timing mode 0 Tcs = 70ns and maximum nand_mp_clk period of 4ns for 1x/4x clock multiple for 16ns cycle time device. spare_area_skip_bytes Spare area skip bytes Module Instance Base Address Register Address nandregs 0xFFB80000 0xFFB80230 Offset: 0x230 Access: NAND Flash Controller Altera Corporation Send Feedback...
Page 893 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. NAND Flash Controller Altera Corporation Send Feedback...
Page 894 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved value RW 0x0 NAND Flash Controller Altera Corporation Send Feedback...
Page 895 (MSB of final row address) has to be sent. The value programmed in this register will be used to mask the address while sending out the last row address. NAND Flash Controller Altera Corporation Send Feedback...
Page 896 This register is used to control the assertion/de-assertion of the WP# pin to the device. Module Instance Base Address Register Address nandregs 0xFFB80000 0xFFB80280 Offset: 0x280 Access: NAND Flash Controller Altera Corporation Send Feedback...
Page 897 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved value RW 0x32 NAND Flash Controller Altera Corporation Send Feedback...
Page 898 16 in the controller to form the final reset wait count. watchdog_reset_count The number of cycles the controller waits before flagging a watchdog timeout interrupt. NAND Flash Controller Altera Corporation Send Feedback...
Page 899 13-82 logical_page_data_size on page 13-82 Logical page data area size in bytes logical_page_spare_size on page 13-83 Logical page data area size in bytes revision on page 13-84 Controller revision number NAND Flash Controller Altera Corporation Send Feedback...
Page 900 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved value RW 0x0 NAND Flash Controller Altera Corporation Send Feedback...
Page 901 RO 0x0 device_id Fields Name Description Access Reset Device ID. This register is updated only for Legacy value NAND devices. device_param_0 Module Instance Base Address Register Address nandregs 0xFFB80000 0xFFB80320 Offset: 0x320 Access: NAND Flash Controller Altera Corporation Send Feedback...
Page 902 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved value RO 0x0 NAND Flash Controller Altera Corporation Send Feedback...
Page 903 Reserved Reserved value RO 0x0 device_param_2 Fields Name Description Access Reset Reserved. value logical_page_data_size Logical page data area size in bytes Module Instance Base Address Register Address nandregs 0xFFB80000 0xFFB80350 Offset: 0x350 Access: NAND Flash Controller Altera Corporation Send Feedback...
Page 904 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved value RO 0x0 NAND Flash Controller Altera Corporation Send Feedback...
Page 905 RO 0x5 revision Fields Name Description Access Reset 15:0 Controller revision number value onfi_device_features Features supported by the connected ONFI device Module Instance Base Address Register Address nandregs 0xFFB80000 0xFFB80380 Offset: 0x380 NAND Flash Controller Altera Corporation Send Feedback...
Page 906 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. NAND Flash Controller Altera Corporation Send Feedback...
Page 907 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved value RO 0x0 NAND Flash Controller Altera Corporation Send Feedback...
Page 908 [*]Bit 4 - Supports Timing mode 4. [*]Bit 5 - Supports Timing mode 5.[/list] onfi_device_no_of_luns Indicates if the device is an ONFI compliant device and the number of LUNS present in the device NAND Flash Controller Altera Corporation Send Feedback...
Page 909 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. NAND Flash Controller Altera Corporation Send Feedback...
Page 910 Bit Fields Reserved value RO 0x0 onfi_device_no_of_blocks_per_lun_u Fields Name Description Access Reset 15:0 Indicates the upper bits of number of blocks per LUN value present in the ONFI complaint device. NAND Flash Controller Altera Corporation Send Feedback...
Page 911 General purpose registers are is present in gpreg hardware. if set, Side band DMA signals are present in hardware. xdma_sideband if set, Partition logic is present in hardware. partition Not implemented. cmd_dma if set, DATA-DMA is present in hardware. NAND Flash Controller Altera Corporation Send Feedback...
Page 912 Interrupt status register for bank 2 intr_en2 on page 13-105 Enables corresponding interrupt bit in interrupt register for bank 2 page_cnt2 on page 13-107 Decrementing page count bank 2 err_page_addr2 on page 13-108 Erred page address bank 2 NAND Flash Controller Altera Corporation Send Feedback...
Page 913 RO 0x0 transfer_mode Fields Name Description Access Reset [list][*]00 - Bank 3 is in Main mode [*]01 - Bank 3 is value3 in Spare mode [*]10 - Bank 3 is in Main+Spare mode[/list] NAND Flash Controller Altera Corporation Send Feedback...
Page 914 RW 0x0 cmd_ RW 0x0 comp intr_status0 Fields Name Description Access Reset For every page of data transfer to or from the device, page_xfer_inc this bit will be set. NAND Flash Controller Altera Corporation Send Feedback...
Page 915 A data DMA command has completed on this bank. dma_cmd_comp RSVD RSVD Ecc logic detected uncorrectable error while reading ecc_uncor_err data from flash device. intr_en0 Enables corresponding interrupt bit in interrupt register for bank 0 NAND Flash Controller Altera Corporation Send Feedback...
Page 916 The address to program or erase operation is to a locked_blk locked block and the operation failed due to this reason NAND Flash Controller Altera Corporation Send Feedback...
Page 917 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. NAND Flash Controller Altera Corporation Send Feedback...
Page 918 Bit Fields Reserved value RO 0x0 err_page_addr0 Fields Name Description Access Reset 15:0 Holds the page address that resulted in a failure on value program or erase operation. NAND Flash Controller Altera Corporation Send Feedback...
Page 919 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. NAND Flash Controller Altera Corporation Send Feedback...
Page 920 A pipeline command or a copyback bank command pipe_cpybck_cmd_comp has completed on this particular bank Device erase operation complete erase_comp Device finished the last issued program command. program_comp Device finished the last issued load command. load_comp NAND Flash Controller Altera Corporation Send Feedback...
Page 921 INT_ unsup locke pipe_ erase progr load_ erase progr time_ dma_ Reser ecc_ xfer_inc cmd_ comp _cmd d_blk cpybc _comp comp _fail cmd_ uncor_ comp fail comp RW 0x0 cmd_ RW 0x0 comp NAND Flash Controller Altera Corporation Send Feedback...
Page 922 Watchdog timer has triggered in the controller due to time_out one of the reasons like device not responding or controller state machine did not get back to idle A data DMA command has completed on this bank. dma_cmd_comp RSVD RSVD NAND Flash Controller Altera Corporation Send Feedback...
Page 923 Maintains a decrementing count of the number of value pages in the multi-page (pipeline and copyback) command being executed. err_page_addr1 Erred page address bank 1 Module Instance Base Address Register Address nandregs 0xFFB80000 0xFFB80490 Offset: 0x490 Access: NAND Flash Controller Altera Corporation Send Feedback...
Page 924 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved value RO 0x0 NAND Flash Controller Altera Corporation Send Feedback...
Page 925 Map 01 page read/write address does not match the corresponding expected address from the pipeline commands issued earlier. The NAND Flash Memory Controller has completed rst_comp its reset and initialization process NAND Flash Controller Altera Corporation Send Feedback...
Page 926 Ecc logic detected uncorrectable error while reading ecc_uncor_err data from flash device. intr_en2 Enables corresponding interrupt bit in interrupt register for bank 2 Module Instance Base Address Register Address nandregs 0xFFB80000 0xFFB804C0 Offset: 0x4C0 NAND Flash Controller Altera Corporation Send Feedback...
Page 927 A pipeline command or a copyback bank command pipe_cpybck_cmd_comp has completed on this particular bank Device erase operation complete erase_comp Device finished the last issued program command. program_comp NAND Flash Controller Altera Corporation Send Feedback...
Page 928 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved Reserved value RO 0x0 NAND Flash Controller Altera Corporation Send Feedback...
Page 929 15:0 Holds the page address that resulted in a failure on value program or erase operation. err_block_addr2 Erred block address bank 2 Module Instance Base Address Register Address nandregs 0xFFB80000 0xFFB804F0 Offset: 0x4F0 NAND Flash Controller Altera Corporation Send Feedback...
Page 930 INT_ unsup locke pipe_ erase progr load_ erase progr time_ dma_ Reser ecc_ xfer_inc cmd_ comp _cmd d_blk cpybc _comp comp _fail cmd_ uncor_ comp fail comp RW 0x0 cmd_ RW 0x0 comp NAND Flash Controller Altera Corporation Send Feedback...
Page 931 Watchdog timer has triggered in the controller due to time_out one of the reasons like device not responding or controller state machine did not get back to idle A data DMA command has completed on this bank. dma_cmd_comp RSVD RSVD NAND Flash Controller Altera Corporation Send Feedback...
Page 932 Map 01 page read/write address does not match the corresponding expected address from the pipeline commands issued earlier. A reset command has completed on this bank rst_comp R/B pin of device transitioned from low to high INT_act NAND Flash Controller Altera Corporation Send Feedback...
Page 933 RSVD RSVD If set, Controller will interrupt processor when Ecc ecc_uncor_err logic detects uncorrectable error. page_cnt3 Decrementing page count bank 3 Module Instance Base Address Register Address nandregs 0xFFB80000 0xFFB80520 Offset: 0x520 Access: NAND Flash Controller Altera Corporation Send Feedback...
Page 934 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved value RO 0x0 NAND Flash Controller Altera Corporation Send Feedback...
Page 935 ECC registers Register Descriptions Offset: 0x650 ECCCorInfo_b01 on page 13-115 ECC Error correction Information register. Controller updates this register when it completes a transaction. The values are held in this register till a new transaction completes. NAND Flash Controller Altera Corporation Send Feedback...
Page 936 A value of zero indicates that no ECC error occurred in last completed transaction. Uncorrectable error occurred while reading pages for uncor_err_b0 last transaction in Bank0. Uncorrectable errors also generate interrupts in intr_statusx register. NAND Flash Controller Altera Corporation Send Feedback...
Page 937 Maximum of number of errors corrected per sector in max_errors_b3 Bank3. This field is not valid for uncorrectable errors. A value of zero indicates that no ECC error occurred in last completed transaction. NAND Flash Controller Altera Corporation Send Feedback...
Page 938 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. NAND Flash Controller Altera Corporation Send Feedback...
Page 939 Bit Fields Reserved Reserved target_ error RW 0x0 dma_intr Fields Name Description Access Reset Controller initiator interface received an ERROR target_error target response for a transaction. NAND Flash Controller Altera Corporation Send Feedback...
Page 940 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. NAND Flash Controller Altera Corporation Send Feedback...
Page 941 Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. Bit Fields Reserved value RO 0x0 target_err_addr_hi Fields Name Description Access Reset 15:0 Most significant 16 bits value flash_burst_length NAND Flash Controller Altera Corporation Send Feedback...
Page 942 If not, the device side burst length will be equal to host side burst length. chip_interleave_enable_and_allow_int_reads NAND Flash Controller Altera Corporation Send Feedback...
Page 943 [*]1 - Enable [*]0 - Disable[/list] This bit informs the controller to enable or disable chip_interleave_ interleaving among banks/LUNS to increase the net enable performance of the controller. [list][*]1 - Enable interleaving [*]0 - Disable Interleaving[/list] no_of_blocks_per_lun NAND Flash Controller Altera Corporation Send Feedback...
Page 944 Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved. NAND Flash Controller Altera Corporation Send Feedback...
Page 945: Document Revision History
Version Changes October 2016 2016.10.28 Added content about the local memory buffer May 2016 2016.05.27 Added a link to the Supported Flash Devices for Cyclone V and Arria V SoC webpage. May 2016 2016.05.03 Maintenance release November 2015 2015.11.02 • Moved "Interface Signals" section after "NAND Flash Controller Block Diagram and System Integration"...
Page 946 December 2013 2013.12.30 Maintenance release November 2012 • Supports one 8-bit device • Show additional supported block sizes • Bad block marker handling May 2012 Added programming model section. January 2012 Initial release NAND Flash Controller Altera Corporation Send Feedback...
Page 947: Features Of The Sd/Mmc Controller
• Integrated descriptor-based direct memory access (DMA) • Internal 4 KB receive and transmit FIFO buffer 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos ©...
Page 948: Sd Card Support Matrix
14-3 For more information on what is supported, refer to the MMC Support Matrix table. Supported Flash Devices for Cyclone V and Arria V SoC • For more information, refer to the supported SD/SDHC/SDXC/MMC/eMMC flash devices section on this page.
Page 949: Mmc Support Matrix
ARM Cortex- A9 microprocessor unit (MPU) subsystem. Supports a maximum clock rate of 50 MHz instead of 52 MHz (specified in MMC specification). (45) (46) Optional 8-bit bus mode not supported in all packages. SD/MMC Controller Altera Corporation Send Feedback...
Page 950: Sd/Mmc Controller Signal Description
Note: The last five signals in the table are not routed to HPS I/O, but only to the FPGA. Table 14-3: SD/MMC Controller Interface I/O Pins Signal Width Direction Description Clock from controller sdmmc_cclk_out to the card sdmmc_cmd_i Card command sdmmc_cmd_o sdmmc_cmd_oe External device power sdmmc_pwr_ena_o enable SD/MMC Controller Altera Corporation Send Feedback...
Page 951: Functional Description Of The Sd/Mmc Controller
† commands. † • Data—transferred serially using the data pins for data movement commands. In the following figure, the clock is a representative only and does not show the exact number of clock cycles. SD/MMC Controller Altera Corporation Send Feedback...
Page 952 The Bus Interface Unit (BIU) interfaces with the Card Interface Unit (CIU), and is connected to the level 3 (L3) interconnect and level 4 (L4) peripheral buses. The BIU consists of the following primary functional blocks, which are defined in the following sections: SD/MMC Controller Altera Corporation Send Feedback...
Page 953 0, the new command is sent to the SD/MMC/CE-ATA card as wait_prvdata_complete soon as the previous command is sent. Typically, use this feature to stop or abort a previous data † transfer or query the card status in the middle of a data transfer. SD/MMC Controller Altera Corporation Send Feedback...
Page 954 In 4-bit mode, if all data bits do not have start bit, then this error is set. † 12 Hardware Locked write Error (HLE) During hardware-lock period, write attempted † to one of locked registers. SD/MMC Controller Altera Corporation Send Feedback...
Page 955 • In Boot Mode: Boot Data Start (BDS) When set, indicates that SD/MMC controller has started to receive boot data from the card. A write to this register with a value of 1 clears † this interrupt. SD/MMC Controller Altera Corporation Send Feedback...
Page 956 † ISR in non-DMA mode: † if (pending_bytes > \ † (FIFO_DEPTH - TX_WMark)) † push (FIFO_DEPTH - \ † TX_WMark) data into FIFO † else † push pending_bytes data \ † into FIFO SD/MMC Controller Altera Corporation Send Feedback...
Page 957 The SDIO Interrupts, Receive FIFO Data Request, and Transmit FIFO Data Request interrupts are set by level-sensitive interrupt sources. Therefore, the interrupt source must be first cleared before you can reset † the interrupt’s corresponding bit in the register to 0. rintsts SD/MMC Controller Altera Corporation Send Feedback...
Page 958 The descriptor list resides in the physical † memory address space of the host. Each descriptor can point to a maximum of two data buffers. SD/MMC Controller Altera Corporation Send Feedback...
Page 959 Data Buffer Descriptor B Data Buffer Descriptor C Internal DMA Controller Descriptor Address The descriptor address must be aligned to the 32-bit bus. Each descriptor contains 16 bytes of control and † status information. SD/MMC Controller Altera Corporation Send Feedback...
Page 960 When set to 1, this bit indicates that the descriptor list reached its final descriptor. The internal DMA controller returns to the base address of the list, creating a descriptor ring. ER is meaningful for only a dual-buffer descriptor structure. SD/MMC Controller Altera Corporation Send Feedback...
Page 961 1 and not buffer 2. † Table 14-8: Internal DMA Controller DES2 Descriptor Field The DES2 descriptor field contains the address pointer to the data buffer. SD/MMC Controller Altera Corporation Send Feedback...
Page 962 If a descriptor is marked as last, the buffer might or might not be full, as † indicated by the buffer size in the DES1 field. The driver is aware of the number of locations that are valid. The driver is expected to ignore the remaining, invalid bytes. SD/MMC Controller Altera Corporation Send Feedback...
Page 963 An interrupt is generated only once for simultaneous, multiple events. The driver must scan the idsts † register for the interrupt cause. The final interrupt signal from the controller is a logical OR of the interrupts from the BIU and internal DMA controller. SD/MMC Controller Altera Corporation Send Feedback...
Page 964 1 and the descriptor is closed by setting the OWN bit in the † DES0 field to 1. † register indicates one of the following conditions: rintsts SD/MMC Controller Altera Corporation Send Feedback...
Page 965 During normal data transfer conditions, FIFO buffer overflow and underflow does not occur. However, if there is a programming error, a FIFO buffer overflow or underflow can result. For example, consider the † following scenarios. SD/MMC Controller Altera Corporation Send Feedback...
Page 966 SD/MMC protocol. The control register values also decide whether the command and data traffic is directed to the CE-ATA card, and the SD/MMC controller † controls the command and data path accordingly. SD/MMC Controller Altera Corporation Send Feedback...
Page 967 BIU that the command is done, and then waits for eight clock cycles before loading a new command. In CE-ATA data payload transfer (RW_MULTIPLE_BLOCK) commands, if the card device interrupts are enabled (the nIEN bit is set to 0 SD/MMC Controller Altera Corporation Send Feedback...
Page 968 0), the command path state machine sends out a command on the card bus. † Figure 14-6: Command Path State Machine load_new_cmd Done Command Idle response_expected = 0 wait_tncc Transmit Command Send IRQ Response Request Response Done/ Receive Response Timeout Response response_expected = 1 SD/MMC Controller Altera Corporation Send Feedback...
Page 969 While accessing a CE-ATA card device, for commands that expect a CCS, the P-bit is driven after the response only if the interrupts are disabled in the CE-ATA card (the nIEN SD/MMC Controller Altera Corporation Send Feedback...
Page 970 CCSs from the card. When the data transfer is over—that is, when the requested number of † bytes are transferred—the bit in the register is set to 1. rintsts SD/MMC Controller Altera Corporation Send Feedback...
Page 971 FIFO buffer during a read data transfer. The data path loads new data parameters—data expected, read/write data transfer, stream/block transfer, block size, byte count, card type, timeout registers—whenever a data transfer command is not in progress. If the data SD/MMC Controller Altera Corporation Send Feedback...
Page 972 STOP command occurs after the last byte of the stream write transfer matches. This data transfer can also † terminate if the host issues a STOP command before all the data bytes are transferred to the card bus. SD/MMC Controller Altera Corporation Send Feedback...
Page 973 If the block size is less than 4, 16, or 32 for card data widths of 1 bit, 4 bits, or 8 bits, respectively, the data transmit state machine terminates the data transfer when all the data is transferred, at which time the † internally-generated STOP command is loaded in the command path. SD/MMC Controller Altera Corporation Send Feedback...
Page 974 STOP command is internally generated and loaded into the command path, where the end bit of the STOP command occurs after the last byte of the stream data transfer is received. This data transfer can SD/MMC Controller Altera Corporation Send Feedback...
Page 975 MMC, and a multiple-block read or write for SD memory transfer for SD cards. The software must set the bit according to the send_auto_stop † following details: † The following list describes conditions for the AUTO_STOP command: SD/MMC Controller Altera Corporation Send Feedback...
Page 976 MMC and SD cards. If byte_count = n*block_size (n = 2, 3, …), the condition is treated as a predefined multiple-block data transfer command. In the case of SD/MMC Controller Altera Corporation Send Feedback...
Page 977 2) Issue CMD18/CMD25 commands without issuing CMD23 command to the card, with the send_auto_stop bit set. In this case, the multiple-block data transfer † is terminated by an internally-generated auto-stop command after the programmed byte count. SD/MMC Controller Altera Corporation Send Feedback...
Page 978 LOCK_ SEND_NUM_ SEND_SCR CSD (CMD27) PROT (CMD30) UNLOCK STATUS WR_BLOCKS (ACMD51) (CMD42) (ACMD1 (ACMD22) † Command Argument register programming Stuff bits 32-bit write Stuff bits Stuff Stuff bits Stuff bits protect data bits address SD/MMC Controller Altera Corporation Send Feedback...
Page 979 Num_bytes = Number of bytes specified as per the lock card data structure. Refer to the SD specification and † the MMC specification. Num_bytes = Number of bytes specified as per the lock card data structure. Refer to the SD specification and (49) † the MMC specification. SD/MMC Controller Altera Corporation Send Feedback...
Page 980: Error Detection
FIFO buffer remains empty for a data-timeout number of clock cycles, the data path signals a data-starvation error to the BIU and the data path † continues to wait for data in the FIFO buffer. SD/MMC Controller Altera Corporation Send Feedback...
Page 981: Clocks
Phase-shifted clock of used to sdmmc_sample_clk sdmmc_clk_divided sample the command and data from the card Internal Phase-shifted clock of for controller sdmmc_drv_clk sdmmc_clk_divided to drive command and data to the card to meet hold time requirements SD/MMC Controller Altera Corporation Send Feedback...
Page 982: Resets
3-1 Taking the SD/MMC Controller Out of Reset When a cold or warm reset is issued in the HPS, the reset manager resets this module and holds it in reset until software releases it. SD/MMC Controller Altera Corporation Send Feedback...
Page 983: Voltage Switching
3.3V. To support these different voltage requirements, external transceivers are needed. The general steps to switch the voltage level requires you to use a SD/MMC voltage-translation transceiver in between the HPS and the SD/MMC card. SD/MMC Controller Altera Corporation Send Feedback...
Page 984 † 3. ACMD 41 is started. The response to this command informs the software if the card supports voltage switching; bits 38, 36, † and 32 are checked by the card argument of ACMD41. SD/MMC Controller Altera Corporation Send Feedback...
Page 985: Sd/Mmc Controller Programming Model
SD/MMC Controller Programming Model † Software and Hardware Restrictions Only one data transfer command should be issued at one time. For CE-ATA devices, if CE-ATA device interrupts are enabled (nIEN=0), only one RW_MULTIPLE_BLOCK command (RW_BLK) should be SD/MMC Controller Altera Corporation Send Feedback...
Page 986 Byte Count register to 0, the DMA logic will likely request more data than it will send to the card, since it has no way of knowing at which point the software will stop the transfer. The DMA request stops as soon † as the DTO is set by the CIU. SD/MMC Controller Altera Corporation Send Feedback...
Page 987: Initialization †
After the power and clock to the controller are stable, the controller active-low reset is asserted. The reset sequence initializes the registers, FIFO buffer pointers, DMA interface controls, and state machines in the † controller. SD/MMC Controller Altera Corporation Send Feedback...
Page 988 † 4. Set the bit of the register to 1. int_enable ctrl Note: Altera recommends that you write 0xFFFFFFFF to the register to clear any pending rintsts † interrupts before setting the bit to 1. int_enable 5. Discover the card stack according to the card type. For discovery, you must restrict the clock frequency to 400 kHz in accordance with SD/MMC/CE-ATA standards.
Page 989 1. Reset the card width 1 or 4 bit ( ) and card width 8 bit ( ) fields in the card_width2 card_width1 ctype register to 0. 2. Identify the card type as SD, MMC, SDIO or SDIO-COMBO: SD/MMC Controller Altera Corporation Send Feedback...
Page 990 Only continue with this step if the SDIO card type is COMBO or there is no response received from the step 5 of the Identifying the Connected Card previous IO_SEND_OP_COND command. Otherwise, skip to Type section. 1. Send the SD/SDIO SEND_IF_COND (CMD8) command with the following arguments: SD/MMC Controller Altera Corporation Send Feedback...
Page 991 Determine whether the card is a CE-ATA v1.1 card device by attempting to select ATA mode. 1. Send the SD/SDIO SEND_IF_COND command, querying byte 504 (S_CMD_SET) of the EXT_CSD register block in the external card. SD/MMC Controller Altera Corporation Send Feedback...
Page 992 9. Set the register of the controller to the correct divider value for the required clock frequency. clkdiv 10.Set the bit of the register to 1, to enable the card clock generation. cclk_enable clkena SD/MMC Controller Altera Corporation Send Feedback...
Page 993: Controller/Dma/Fifo Buffer Reset Usage
0. Note: Ensure that the DMA is idle before performing a DMA reset. Otherwise, the L3 interconnect might † be left in an indeterminate state. Altera recommends setting the , and bits in the register...
Page 994 Choose the value based on the speed mode used. use_hold_reg Indicates that the command is not a clock update update_clk_regs_only command Indicates that the command is not a data data_expected command For one card card_number SD/MMC Controller Altera Corporation Send Feedback...
Page 995: Data Transfer Commands
Before sending a command on the command line, wait_prvdata_complete the host must wait for completion of any data command already in process. Altera recommends that you set this bit to 1, unless the current command is to query status or stop data transfer when transfer is in progress.
Page 996 3. If the read round trip delay, including the card delay, is greater than half of , write sdmmc_clk_divided to the card threshold control register ( ) to ensure that the card clock does not stop in the cardthrctl SD/MMC Controller Altera Corporation Send Feedback...
Page 997 In both cases, the software must read data from the FIFO buffer and make space in the FIFO buffer for † receiving more data. 8. When a DTO interrupt is received, the software must read the remaining data from the FIFO buffer. † SD/MMC Controller Altera Corporation Send Feedback...
Page 998 This bit resets itself to 0 after the command is start_cmd committed. 1 or 0 Choose the value based on speed mode used. use_hold_reg Does not need to update clock parameters update_clk_regs_only Data command data_expected For one card card_number Block transfer transfer_mode SD/MMC Controller Altera Corporation Send Feedback...
Page 999 SINGLE_BLOCK (CMS17) or READ_ MULTIPLE_BLOCK (CMD18) Related Information Auto-Stop on page 14-29 Refer to this table for information about setting the parameter. send_auto_stop Single-Block or Multiple-Block Write The following steps comprise a single-block or multiple-block write: SD/MMC Controller Altera Corporation Send Feedback...
Page 1000 This bit resets itself to 0 after the command is committed start_cmd (accepted by the BIU). 1 or 0 Choose the value based on speed mode used. use_hold_reg Does not need to update clock parameters update_clk_regs_only SD/MMC Controller Altera Corporation Send Feedback...

Altera cyclone V Technical Reference

Introduction to the Hard Processor System

Clock Manager

Reset Manager

FPGA Manager

System Manager

Scan Manager

System Interconnect

HPS-FPGA Bridges

Cortex-A9 Microprocessor Unit Subsystem

Coresight Debug and Trace

SDRAM Controller Subsystem

On-Chip Memory

NAND Flash Controller

SD/MMC Controller

Quad SPI Flash Controller

DMA Controller

Ethernet Media Access Controller

USB 2.0 OTG Controller

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Summary of Contents for Altera cyclone V