Altera cyclone V Technical Reference page 897

13-76
re_2_re
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
write_protect Fields
Bit
0
flag
re_2_re
Timing parameter between re high to re low (Trhz) for the next bank
Module Instance
nandregs
Offset:
0x290
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
When the controller is in reset, the WP# pin is always
asserted to the device. Once the reset is removed, the
WP# is de-asserted. The software will then have to
come and program this bit to assert/de-assert the
same. [list][*]1 - Write protect de-assert [*]0 - Write
protect assert[/list]
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
0xFFB80000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
21 20 19 18
5 4 3 2
Access
Register Address
0xFFB80290
21 20 19 18
5 4 3 2
value
RW 0x32
NAND Flash Controller
cv_5v4
2016.10.28
17 16
1 0
flag
RW 0x1
Reset
RW 0x1
17 16
1 0
Send Feedback