Altera cyclone V Technical Reference page 176

cv_5v4
2016.10.28
Bit
3
crc
2
id
1
cd
0
ns
gpio_int_polarity
Controls the polarity of interrupts that can occur on each GPIO input.
Module Instance
fpgamgrregs
Offset:
0x83C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
FPGA Manager
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Name
Controls whether the level of CRC_ERROR or an
edge on CRC_ERROR generates an interrupt.
Value
0x0
0x1
Controls whether the level of INIT_DONE or an edge
on INIT_DONE generates an interrupt.
Value
0x0
0x1
Controls whether the level of CONF_DONE or an
edge on CONF_DONE generates an interrupt.
Value
0x0
0x1
Controls whether the level of nSTATUS or an edge on
nSTATUS generates an interrupt.
Value
0x0
0x1
0xFF706000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Description
Level-sensitive
Edge-sensitive
Description
Level-sensitive
Edge-sensitive
Description
Level-sensitive
Edge-sensitive
Description
Level-sensitive
Edge-sensitive
Base Address
0xFF70683C
4-33
gpio_int_polarity
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
Register Address
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