Altera cyclone V Technical Reference page 141

3-30
miscmodrst
and are de-asserted in the correct order. It is also up to software to not assert a module reset signal that
would prevent software from de-asserting the module reset signal. For example, software should not assert
the module reset to the CPU executing the software. Software writes a bit to 1 to assert the module reset
signal and to 0 to de-assert the module reset signal. All fields are only reset by a cold reset
Module Instance
rstmgr
Offset:
0x20
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
tapcold dbg sysdb
RW 0x0 RW
0x0
miscmodrst Fields
Bit
16
sdrcold
15
tapcold
14
dbg
13
sysdbg
12
frzctrlcold
11
scanmgr
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
frzct scanm clkmg
g rlcol gr rcold
d
RW RW RW
0x0 RW 0x0 0x0
0x0
Name
Resets logic in SDRAM Controller Subsystem affected
only by a cold reset.
Resets portion of DAP JTAG TAP controller no reset
by a debug probe reset (i.e. nTRST pin). Cold reset
only.
Resets logic located only in the debug domain.
Resets logic that spans the system and debug
domains.
Resets Freeze Controller in System Manager (cold
reset only)
Resets Scan Manager
Base Address
0xFFD05000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
times nrstp s2fco s2f
tampc in ld
RW
old
RW RW 0x0
RW 0x0 0x0
0x0
Description
Register Address
0xFFD05020
21 20 19 18
5 4 3 2
acpid fpgam sysmg sysmg
map gr rcold r
RW RW RW RW
0x0 0x0 0x0 0x0
cv_5v4
2016.10.28
17 16
sdrcold
RW 0x0
1 0
ocram rom
RW RW 0x0
0x0
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
Reset Manager
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