Dma Controller Address Map And Register Definitions - Altera cyclone V Technical Reference

16-60

DMA Controller Address Map and Register Definitions

Figure 16-35: Fixed Destination with Aligned Address
Each
DMALD
address is a 32-bit fixed address, then the DMAC splits each 64-bit data item across two entries in the
MFIFO buffer.
This example has a static requirement of zero MFIFO buffer entries and a dynamic requirement of four
MFIFO buffer entries.
DMA Controller Address Map and Register Definitions
The following DMAC register map spans a 4 KB region, consists of the following sections.
Altera Corporation
in the program loads two 64-bit data transfers into the MFIFO buffer. Because the destination
4 a a a
0
b b b
DMALD
a 7
a a a a
a a a a
a a a a
a a a a
b
DMAST
Data from
DMALD
0
Data for
DMAST
DMA Controller
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cv_5v4
2016.10.28