Altera cyclone V Technical Reference page 623

cv_5v4
2016.10.28
comp_id_0
Component ID0
Module Instance
lwhps2fpgaregs
Offset:
0x1FF0
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
comp_id_0 Fields
Bit
7:0
preamble
comp_id_1
Component ID1
Module Instance
lwhps2fpgaregs
Offset:
0x1FF4
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
HPS-FPGA Bridges
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0xFF400000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Preamble
0xFF400000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
comp_id_0
Register Address
0xFF401FF0
21 20 19 18
5 4 3 2
preamble
RO 0xD
Access
Register Address
0xFF401FF4
8-41
17 16
1 0
Reset
RO 0xD
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