Transmit And Receive Data Fifo Buffers - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

Transmit and Receive Data FIFO Buffers

Each EMAC component has associated transmit and receive data FIFO buffers to regulate the frames
between the application system memory and the EMAC. Both FIFO buffer instances are 1024 x 42 bits.
The FIFO buffer word consists of:
• Data: 32 bits
• Sideband:
• Byte enables: 2 bits
• End of frame (EOF): 1 bit
• Error correction code (ECC): 7 bits
The data and sideband are protected by the 7-bit single error correct, double error detect (SECDED) code
word.
The FIFO buffer RAMs have ECC enable, error injection and status pins. The enable and error injection
pins are inputs driven by the system manager. The status pins are outputs driven to the MPU subsystem.
Note: The ECC block provides outputs to notify the system manager when single-bit correctable errors
are detected (and corrected) and when double-bit uncorrectable errors are detected. The ECC logic
also allows the injection of single-bit and double-bit errors for test purposes.
TX FIFO
The time at which data is sent from the TX FIFO to the EMAC is dependent on the transfer mode
selected:
• Cut-through mode: Data is popped from the TX FIFO when the number of bytes in the TX FIFO
crosses the configured threshold level (or when the end of the frame is written before the threshold is
crossed). The threshold level is configured using the
Note: After more than 96 bytes (or 548 bytes in 1000 Mbps mode) are popped to the EMAC, the TX
FIFO controller frees that space and makes it available to the DMA and a retry is not possible.
• Store-and-Forward mode: Data is popped from the TX FIFO when one or more of the following
conditions are true:
• A complete frame is stored in the FIFO
• The TX FIFO becomes almost full
The application can flush the TX FIFO of all contents by setting bit 20 (
Mode Register). This bit is self-clearing and initializes the FIFO pointers to the default state. If the
is set during a frame transfer to the EMAC, further transfers are stopped because the FIFO is considered
empty. This cessation causes an underflow event and a runt frame to be transmitted and the corresponding
status word is forwarded to the DMA.
If a collision occurs in half-duplex mode operation before an end of the frame, a retry attempt is sent
before the end of the frame is transferred. When notified of the retransmission, the MAC pops the frame
from the FIFO again.
Note: Only packets of 3800 bytes or less can be supported when the checksum offload feature is enabled
by software.
RX FIFO
Frames received by the EMAC are pushed into the RX FIFO. The fill level of the RX FIFO is indicated to
the DMA when it crosses the configured receive threshold which is programmed by the
Ethernet Media Access Controller
Send Feedback
Transmit and Receive Data FIFO Buffers
bit of Register 0 (Bus Mode Register).
TTC
) of Register 6 (Operation
FTF
17-15
bit
FTF
field of
RTC
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