Altera cyclone V Technical Reference page 104

cv_5v4
2016.10.28
Bit
0
bwadjen
ddrdqsclk
Contains settings that control clock ddr_dqs_clk generated from the C0 output of the SDRAM PLL. Fields
are only reset by a cold reset.
Module Instance
clkmgr
Offset:
0xC8
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Clock Manager
Send Feedback
Name
If set to 1, the Loop Bandwidth Adjust value comes
from the Loop Bandwidth Adjust field. If set to 0, the
Loop Bandwidth Adjust value equals the M field
divided by 2 value of the VCO Control Register. The
M divided by 2 is the upper 12 bits (12:1) of the M
field in the VCO register.
0xFFD04000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
Reserved
13 12 11 10
phase
RW 0x0
Description
Base Address
Bit Fields
25 24 23 22
9 8 7 6
ddrdqsclk
Access
Register Address
0xFFD040C8
21 20 19 18
phase
RW 0x0
5 4 3 2
cnt
RW 0x1
2-67
Reset
RW 0x0
17 16
1 0
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