Altera cyclone V Technical Reference page 769

cv_5v4
2016.10.28
Name
ACLK
AWID
AWADDR
AWLEN
AWSIZE
AWBURST
AWLOCK
AWCACHE
AWPROT
AWREADY
AWVALID
WID
32, 64, 128
WDATA
4, 8, 16, 32
WSTRB
WLAST
WVALID
WREADY
BID
BRESP
BVALID
BREADY
ARID
ARADDR
ARLEN
ARSIZE
ARBURST
ARLOCK
SDRAM Controller Subsystem
Send Feedback
Bits Direction
1 In
4 In
32 In
4 In
3 In
2 In
2 In
4 In
3 In
1 Out
1 In
4 In
In
or 256
In
1 In
1 In
1 Out
4 Out
2 Out
1 Out
1 In
4 In
32 In
4 In
3 In
2 In
2 In
Channel
n/a Clock
Write address Write identification tag
Write address Write address
Write address Write burst length
Write address Width of the transfer size
Write address Burst type
Write address Lock type signal which indicates if the
access is exclusive; valid values are 0x0
(normal access) and 0x1 (exclusive access)
Write address Cache policy type
Write address Protection-type signal used to indicate
whether a transaction is secure or non-
secure
Write address Indicates ready for a write command
Write address Indicates valid write command.
Write data Write data transfer ID
Write data Write data
Write data Byte-based write data strobe. Each bit
width corresponds to 8 bit wide transfer for
32-bit wide to 256-bit wide transfer.
Write data Last transfer in a burst
Write data Indicates write data and strobes are valid
Write data Indicates ready for write data and strobes
Write response Write response transfer ID
Write response Write response status
Write response Write response valid signal
Write response Write response ready signal
Read address Read identification tag
Read address Read address
Read address Read burst length
Read address Width of the transfer size
Read address Burst type
Read address Lock type signal which indicates if the
access is exclusive; valid values are 0x0
(normal access) and 0x1 (exclusive access)
11-31
AXI Port
Function
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