Mfifo Buffer Usage Overview - Altera cyclone V Technical Reference

16-52

MFIFO Buffer Usage Overview

Syntax
SS Source burst size in bits. Sets the value of
arsize[2:0]
SB Source burst length. Sets the value of
SP Source protection
SC Source cache
DA Destination address increment. Sets the value of
awburst[0]
DS Destination burst size in bits. Sets the value of
awsize[2:0]
DB Destination burst length. Sets the value of
awlen[3:0]
DP Destination protection
DC Destination cache
ES Endian swap size, in bits
MFIFO Buffer Usage Overview
About MFIFO Buffer Usage Overview
The MFIFO buffer is a shared resource that is utilized on a first-come, first-served basis by all currently
active channels. To a program, it appears as a set of variable-depth parallel FIFO buffers, one per channel,
with the restriction that the total depth of all the FIFOs cannot exceed the size of the MFIFO, which is 512
entries. The width of the AXI master interface is the same as the MFIFO buffer width.
The DMAC is capable of realigning data from the source to the destination. For example, the DMAC shifts
the data by two byte lanes when it reads a word from address 0x103 and writes to address 0x205. All byte
manipulations occur when data enters the MFIFO buffer, as a result of an AXI read due to a
instruction, so that the DMAC does not need to manipulate the data when it removes it from the MFIFO
buffer, as a result of an AXI write due to a
in the MFIFO buffer is determined by the destination address and transfer characteristics.
(56) You must use decimal values when programming this immediate value.
(57) Because the DMAC ties ARCACHE[3] low, the assembler always sets bit 3 to 0 and uses bits [2:0] of your
chosen value for SC.
Because the DMAC ties AWCACHE[2] low, the assembler always sets bit 2 to 0 and uses bit [3] and bits [1:0]
(58)
of your chosen value for DC.
Altera Corporation
Description
arlen[3:0]
instruction. Therefore the storage and packing of the data
DMAST
Options
8, 16, 32, or 64
1 to 16
0 to 7 (56)
0 to 15
(56)(57)
I = Increment
F = Fixed
8, 16, 32, or 64
1 to 16
0 to 7 (56)
0 to 15 (56)(58)
8, 16, 32, or 64
cv_5v4
2016.10.28
Default
8
1
0
0
I
8
1
0
0
8
DMALD
DMA Controller
Send Feedback