Altera cyclone V Technical Reference page 670

9-34
Fixed Mapping Mode
Fixed Mapping Mode
In fixed mode, output IDs 2 through 6 can be assigned by software to specific 12-bit input IDs. This ability
makes it possible to use the lock-by-master feature of the L2 cache controller, because the input transac‐
tion ID from the master is always assigned to a specific output ID. ID 7 is not available for fixed mapping
because it is reserved for dynamic mode only to avoid system deadlocks.
The ACP ID mapper can control the behavior of read and write virtual fixed ID mappings through the
and
vid*rd
the 12-bit
and write AXI Master Mapping registers. When these registers are programmed, hardware examines the
request, and only applies the change when safe to do so, which is when there are no outstanding transac‐
tions with the output ID. When the change is applied, the status register is updated. Software should check
that the change has actually taken place by polling the corresponding status register.
HPS Peripheral Master Input IDs
The following table identifies the ID that must be programmed in the
registers, if an HPS master requires a fixed ACP mapping. The first column of the table gives the generic
ID encoding, where the "x"s represent bits that change based on if the
configured.
Table 9-8: HPS Peripheral Master Input IDs
The input IDs issued by the interconnect for each HPS peripheral master that can access the ACP ID
mapper
Interconnect
Master
DMA
(23) Values are in binary. The letter
Altera Corporation
registers. By programming the
vid*wr
field is forced to a specific 3-bit virtual ID. The
mid
ID (23)
"
x
0000 0xxx x001
number of DMA channels. When
the DMA performs an ACP read,
the DMA controller signals the
values to be the same number as
the number of DMA channels that
the DMA controller provides. For
example, if the DMA controller
provides eight DMA channels, the
x
denotes variable ID bits that each master passes with each transaction.
x
bit to 0x1 in the
force
vid*rd.mid
" should indicate the total
values must be set to
4'b1000
and
vid*rd
field can be different between the read
mid
field of the
mid vid*rd
or
vid*rd vid*wr
vid*wr.mid
" " should indicate the number
x
of the channel performing the
write. When a DMA channel
performs and an ACP write, the
x
DMA controller signals the
values to be the same number
as the DMA channel. For
example, when DMA channel 5
performs a DMA store
. operation, the DMA Controller
sets the values to
x
Cortex-A9 Microprocessor Unit Subsystem
cv_5v4
2016.10.28
registers,
vid*wr
and
vid*wr
register is being
x
.
4'b0101
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