Altera cyclone V Technical Reference page 51

2-14
Flash Controller Clocks
System Clock Name
emac1_clk
l4_mp_clk
l4_sp_clk
can0_clk
can1_clk
gpio_db_clk
h2f_user1_clock
Flash Controller Clocks
Flash memory peripherals can be driven by the main PLL, the peripheral PLL, or from clocks provided by
the FPGA fabric.
Figure 2-5: Flash Peripheral Clock Divide and Gating
f2h_periph_ref_clk
main_nand_sdmmc_base_clk
periph_nand_sdmmc_base_clk
f2h_periph_ref_clk
main_nand_sdmmc_base_clk
periph_nand_sdmmc_base_clk
f2h_periph_ref_clk
main_qspi_base_clk
periph_qspi_base_clk
Altera Corporation
Frequency
Up to 250 MHz
Up to 100 MHz
Up to 100 MHz
Up to 100 MHz
Up to 100 MHz
Up to 1 MHz
Peripheral PLL C5
Clock Gate
Clock Gate
Clock Gate
Divided From
Peripheral PLL C1
Main PLL C1 or peripheral
PLL C4
Main PLL C1 or peripheral
PLL C4
Peripheral PLL C4
Peripheral PLL C4
Peripheral PLL C4
Peripheral PLL C5
Divide by 4
2016.10.28
Constraints and Notes
EMAC1 clock
The 250 MHz clock is
divided internally by
the EMAC into the
typical 125/25/2.5 MHz
speeds for 1000/100/
10 Mbps operation.
Clock for L4 master
peripheral bus
Clock for L4 slave
peripheral bus
Controller area
network (CAN)
controller 0 clock
CAN controller 1 clock
Used to debounce
GPIO0, GPIO1, and
GPIO2
Auxiliary user clock to
the FPGA fabric
sdmmc_clk
nand_x_clk
Clock Gate nand_clk
qspi_clk
Clock Manager
Send Feedback
cv_5v4