Sdram Controller Subsystem Interfaces - Altera cyclone V Technical Reference

11-4

SDRAM Controller Subsystem Interfaces

Memory Type
(25)
1024 (1 Gb) -
LPDDR2
1024 (1 Gb) -
(2 Gb) - S2
(2 Gb) -S4
SDRAM Controller Subsystem Interfaces
MPU Subsystem Interface
The SDRAM controller connects to the MPU subsystem with a dedicated 64-bit AXI interface, operating
on the
mpu_l2_ram_clk
L3 Interconnect Interface
The SDRAM controller interfaces to the L3 interconnect with a dedicated 32-bit AXI interface, operating
on the
l3_main_clk
Related Information
System Interconnect
For all memory types shown in this table, the DQ width is 8.
(25)
S2 signifies a 2n prefetch size
(26)
(27) S4 signifies a 4n prefetch size
Altera Corporation
Mbits Column
Address Bit
Width
64 9
128 10
256 10
512 11
11
S2
(26)
11
S4 (27)
2048
11
(26)
2048
11
(27)
4096
12
(4 Gb)
clock domain.
clock domain.
on page 7-1
Row Address
Bank Select
Bit Width
Bit Width
2 12
2 12
2 13
2 13
2 14
3 13
2 15
3 14
3 14
Page Size MBytes
512
1024
1024
2048
2048
2048
2048
2048
4096
SDRAM Controller Subsystem
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cv_5v4
2016.10.28
8
16
32
64
128
128
256
256
512