Usb Otg Controller Block Diagram And System Integration - Altera cyclone V Technical Reference

18-4

USB OTG Controller Block Diagram and System Integration

USB OTG Controller Block Diagram and System Integration
Figure 18-1: USB OTG Controller System Integration
Two subsystems are included in the HPS.
The USB OTG controller connects to the level 3 (L3) interconnect through a slave interface, allowing other
masters to access the control and status registers (CSRs) in the controller. The controller also connects to
the L3 interconnect through a master interface, allowing the DMA engine in the controller to move data
between external memory and the controller.
A single-port RAM (SPRAM) connected to the USB OTG controller is used to store USB data packets for
both host and device modes. It is configured as FIFO buffers for receive and transmit data packets on the
USB link.
Through the system manager, the USB OTG controller has control to use and test error correction codes
(ECCs) in the SPRAM. Through the system manager, the USB OTG controller can also control the
behavior of the master interface to the L3 interconnect.
The USB OTG controller connects to the external USB transceiver through a ULPI PHY interface. This
interface also connects through pin multiplexers within the HPS. The pin multiplexers are controlled by
the system manager.
Altera Corporation
Bus Control
System
ECC Control
Manager
IRQ
Clock
Reset
L3 Interconnect
Master
Interface
SPRAM
External USB Transceiver
Slave
Interface
USB OTG
Controller
ULPI PHY
Interface
USB 2.0 OTG Controller
Send Feedback
cv_5v4
2016.10.28