Altera cyclone V Technical Reference page 936

Hard processor system
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cv_5v4
2016.10.28
ECCCorInfo_b23
ECC Error correction Information register. Controller updates this register when it completes a
transaction. The values are held in this register till a new transaction completes.
ECCCorInfo_b01
ECC Error correction Information register. Controller updates this register when it completes a
transaction. The values are held in this register till a new transaction completes.
Module Instance
nandregs
Offset:
0x650
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
15
14
uncor_
err_b1
RO 0x0
ECCCorInfo_b01 Fields
Bit
15
uncor_err_b1
14:8
max_errors_b1
7
uncor_err_b0
NAND Flash Controller
Send Feedback
on page 13-116
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
max_errors_b1
RO 0x0
Name
Uncorrectable error occurred while reading pages for
last transaction in Bank1. Uncorrectable errors also
generate interrupts in intr_statusx register.
Maximum of number of errors corrected per sector in
Bank1. This field is not valid for uncorrectable errors.
A value of zero indicates that no ECC error occurred
in last completed transaction.
Uncorrectable error occurred while reading pages for
last transaction in Bank0. Uncorrectable errors also
generate interrupts in intr_statusx register.
Base Address
Bit Fields
25
24
23
22
Reserved
9
8
7
6
uncor
_err_
b0
RO
0x0
Description
ECCCorInfo_b01
Register Address
0xFFB80650
21
20
19
18
5
4
3
2
max_errors_b0
RO 0x0
Access
13-115
17
16
1
0
Reset
RO
0x0
RO
0x0
RO
0x0
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