Memory Protection - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
AXI-Exclusive Support
The single-port controller supports AXI-exclusive operations. The controller implements a table shared
across all masters, which can store up to 16 pending writes. Table entries are allocated on an exclusive read
and table entries are deallocated on a successful write to the same address by any master.
Any exclusive write operation that is not present in the table returns an exclusive fail as acknowledgement
to the operation. If the table is full when the exclusive read is performed, the table replaces a random entry.
Note: When using AXI-exclusive operations, accessing the same location from Avalon-MM interfaces can
result in unpredictable results.

Memory Protection

The single-port controller has address protection to allow the software to configure basic protection of
memory from all masters in the system. If the system has been designed exclusively with AMBA masters,
TrustZone
®
Memory protection is based on physical addresses in memory. The single-port controller can configure up
to 20 rules to allow or prevent masters from accessing a range of memory based on their AxIDs, level of
security and the memory region being accessed. If no rules are matched in an access, then default settings
take effect.
The rules are stored in an internal protection table and can be accessed through indirect addressing offsets
in the
protruledwr
appropriate offset in the
To write a new rule, three registers in the CSR must be configured:
1. The
protportdefault
when no rules match. When a bit is clear, all default accesses from that port pass. When a bit is set, all
default accesses from that port fails. The bits are assigned as follows:
Table 11-7:
protportdefault
Bits
31:10
9
8
7
6
SDRAM Controller Subsystem
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is supported. Ports that use Avalon-MM can be configured for port level protection.
register in the CSR. To read a specific rule, set the
field of the
ruleoffset
register is programmed to control the default behavior of memory accesses
register
reserved
When this bit is set to 1, deny CPU writes during a default transaction.
When this bit is clear, allow CPU writes during a default transaction.
When this bit is set to 1, deny L3 writes during a default transaction.
When this bit is clear, allow L3 writes during a default transaction.
When this bit is set to 1, deny CPU reads during a default transaction.
When this bit is clear, allow CPU reads during a default transaction.
When this bit is set to 1, deny L3 reads during a default transaction.
When this bit is clear, allow L3 reads during a default transaction.
readrule
register.
protruledwr
Description
11-19
AXI-Exclusive Support
bit and write the
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