Altera cyclone V Technical Reference page 853

13-32
Set Up a Single Area for Pipeline Write-Ahead
controller maintains cache or multi-plane command sequences for continuous streaming of data into the
flash device.
For pipeline write commands, if any page program results in a failure in the device, a
interrupt is issued. The failing page's block and page addresses are updated in the
err_page_addr0
Set Up a Single Area for Pipeline Write-Ahead
To set up an area for pipeline write-ahead:
1. Write to the command register, setting the
address of the block to pre-write.
2. Write 0x21<PP> to the
is the number of pages to pre-write. The pages must not cross a block boundary. If a block boundary is
crossed, the NAND flash controller generates an unsupported command (
drops the command.
After you set up the write-ahead, use a MAP01 command to write the data. In the MAP01 command,
specify the same starting address as in the write-ahead.
If the write command received following a pipeline write-ahead request is not to a pre-written page, then
an interrupt bit is set to 1 and the pipeline read-ahead or write-ahead registers are cleared. You must issue
a new pipeline write-ahead request to configure the write logic.
You must use MAP01 commands to write all of the data that is pre-written before the NAND flash
controller returns to the idle state.
Other Supported Commands
MAP01 commands must read or write pages in the same sequence that the pipelined commands were
issued to the NAND flash controller. If the host issues multiple pipeline commands, pages must be read or
written in the order the pipeline commands were issued. It is not possible to read or write pages for a
second pipeline command before completing the first pipeline command. If the pipeline sequence is
broken by a MAP01 command, the
pipeline command queue. The flash controller services the violating incoming MAP01 read or write
request with a normal page read or write sequence.
For a multi-plane device that supports multi-plane programming, you must set the
multiplane_operation
page-size chunks to consecutive blocks.
A
pipe_cpyback_cmd_comp
processing a pipeline command and has discarded that command from its queue. At this point of time, the
host can send another pipeline command. A pipeline command is popped from the queue, and an
interrupt is issued when the flash controller has started processing the last page of pipeline command.
Hence, the
read command and start of data transfer of the last page to be programmed, in the case of a pipeline write
command.
An additional
the case of a pipeline write command.
Altera Corporation
registers in the
status
register, where the value 1 sets this command as a write-ahead and <PP>
Data
register in the
interrupt is generated when the NAND flash controller has finished
pipe_cpyback_cmd_comp
interrupt is generated when the last page program operation completes in
program_comp
group.
field to 2 and the
CMD_MAP
interrupt is issued, and the flash controller clears the
pipe_cmd_err
group to 1. In this case, the data is interleaved into
config
interrupt is issued prior to the last page load in the case of a pipeline
program_fail
err_block_addr0
field to the starting
BLK_ADDR
) interrupt and
unsup_cmd
bit of the
flag
NAND Flash Controller
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2016.10.28
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