Single-Port Controller Operation - Altera cyclone V Technical Reference

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Single-Port Controller Operation

must wait for its timers to be eligible for execution. Next, the transaction arbitrates against other
transactions that are also eligible for execution.
The following rules govern transaction arbitration:
• High-priority operations take precedence over lower-priority operations
• If multiple operations are in arbitration, read operations have precedence over write operations
• If multiple operations still exist, the oldest is served first
A high-priority transaction in the SDRAM burst scheduler wins arbitration for that bank immediately if
the bank is idle and the high-priority transaction's chip select, row, or column fields of the address do not
match an address already in the single-port controller. If the bank is not idle, other operations to that bank
yield until the high-priority operation is finished. If the chip select, row, and column fields match an
earlier transaction, the high-priority transaction yields until the earlier transaction is completed.
Clocking
The FPGA fabric ports of the MPFE can be clocked at different frequencies. Synchronization is maintained
by clock-domain crossing logic in the MPFE. Command ports can operate on different clock domains, but
the data ports associated with a given command port must be attached to the same clock as that command
port.
Note: A command port paired with a read and write port to form an Avalon-MM interface must operate
at the same clock frequency as the data ports associated with it.
Single-Port Controller Operation
The single-port controller increases the performance of memory transactions through command and data
re-ordering, enforcing bank policies, combining write operations and allowing burst transfers. Correction
of single-bit errors and detection of double-bit errors is handled in the ECC module of the single-port
Controller.
SDRAM Interface
The SDRAM interface is up to 40 bits wide and can accommodate 8-bit, 16-bit, 16-bit plus ECC, 32-bit, or
32-bit plus ECC configurations, depending on the device package. The SDRAM interface supports
LPDDR2, DDR2, and DDR3 memory protocols.
Command and Data Reordering
The heart of the SDRAM controller is a command and data reordering engine. Command reordering
allows banks for future transactions to be opened before the current transaction finishes.
Data reordering allows transactions to be serviced in a different order than they were received when that
new order allows for improved utilization of the SDRAM bandwidth. Operations to the same bank and
row are performed in order to ensure that operations which impact the same address preserve the data
integrity.
The following figure shows the relative timing for a write/read/write/read command sequence performed
in order and then the same command sequence performed with data reordering. Data reordering allows
the write and read operations to occur in bursts, without bus turnaround timing delay or bank reassign‐
ment.
Altera Corporation
cv_5v4
2016.10.28
SDRAM Controller Subsystem
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