Altera cyclone V Technical Reference page 300

5-106
Pin Mux Control Group Register Descriptions
GPLMUX66
Selection between GPIO and LoanIO output and output enable for GPIO66 and LoanIO66. These signals
drive the Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings
Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO
configuration.There is no support for dynamically changing the Pin Mux selections.
GPLMUX67
Selection between GPIO and LoanIO output and output enable for GPIO67 and LoanIO67. These signals
drive the Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings
Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO
configuration.There is no support for dynamically changing the Pin Mux selections.
GPLMUX68
Selection between GPIO and LoanIO output and output enable for GPIO68 and LoanIO68. These signals
drive the Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings
Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO
configuration.There is no support for dynamically changing the Pin Mux selections.
GPLMUX69
Selection between GPIO and LoanIO output and output enable for GPIO69 and LoanIO69. These signals
drive the Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings
Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO
configuration.There is no support for dynamically changing the Pin Mux selections.
GPLMUX70
Selection between GPIO and LoanIO output and output enable for GPIO70 and LoanIO70. These signals
drive the Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings
Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO
configuration.There is no support for dynamically changing the Pin Mux selections.
NANDUSEFPGA
Selection between HPS Pins and FPGA Interface for NAND signals. Only reset by a cold reset (ignores
warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for
dynamically changing the Pin Mux selections.
RGMII1USEFPGA
Selection between HPS Pins and FPGA Interface for RGMII1 signals. Only reset by a cold reset (ignores
warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for
dynamically changing the Pin Mux selections.
I2C0USEFPGA
Selection between HPS Pins and FPGA Interface for I2C0 signals. Only reset by a cold reset (ignores warm
reset). NOTE: These registers should not be modified after IO configuration.There is no support for
dynamically changing the Pin Mux selections.
RGMII0USEFPGA
Selection between HPS Pins and FPGA Interface for RGMII0 signals. Only reset by a cold reset (ignores
warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for
dynamically changing the Pin Mux selections.
I2C3USEFPGA
Selection between HPS Pins and FPGA Interface for I2C3 signals. Only reset by a cold reset (ignores warm
reset). NOTE: These registers should not be modified after IO configuration.There is no support for
dynamically changing the Pin Mux selections.
Altera Corporation
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cv_5v4
2016.10.28
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