Dma Controller Programming Model - Altera cyclone V Technical Reference

16-34
AXI Burst Types
AXI Burst Types
You can program the DMAC to generate only fixed-address or incrementing-address burst types for data
accesses. It does not generate wrapping-address bursts for data accesses or for instruction fetches.
AXI Write Addresses
The DMAC can issue up to eight outstanding write addresses. The DMAC does not issue a write address
until it has read in all of the data bytes required to fulfill that write transaction.
AXI Write Data Interleaving
The DMAC does not generate interleaved write data. All write data beats for one write transaction are
output before any write data beat for the next write transaction.

DMA Controller Programming Model

Instruction Syntax Conventions
The following conventions are used in assembler syntax prototype lines and their subfields:
• - Any item bracketed by < and > is mandatory. A description of the item and of how it is encoded
< >
in the instruction is supplied by subsequent text.
• - Any item bracketed by [ and ] is optional. A description of the item and of how its presence or
[ ]
absence is encoded in the instruction is supplied by subsequent text.
• (spaces) - To separate items, single spaces are used for clarity. When a space is obligatory in the
" "
assembler syntax, two or more consecutive spaces are used.
Instruction Set Summary
The DMAC instructions:
• Indicate a DMA prefix, to provide a unique name-space
• Have 8-bit opcodes that might use a variable data payload of 0, 8, 16, or 32 bits
• Indicate suffixes that are consistent.
Table 16-5: Instruction Syntax Summary
Mnemonic
DMAADDH
DMAADNH
DMAEND
DMAFLUSHP
Altera Corporation
Instruction DMA Manager
Add Halfword No
Add Negative No
Halfword
End Yes
Flush and Notify No
Peripheral
DMA Channel
Usage Usage
Yes
Yes
Yes
Yes
2016.10.28
Description
DMAADDH on page 16-
36
DMAADNH
on page 16-
36
DMAEND
on page 16-
37
DMAFLUSHP
on page
16-37
DMA Controller
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