Altera cyclone V Technical Reference page 696

9-60
dynwr_s
31 30
15 14
Reserved
dynrd_s Fields
Bit
13:12
page
8:4
user
dynwr_s
The Write AXI Master Mapping Status Register contains the configured USER, and ADDR page signals
mapping values for transaction that dynamically remapped to one of the available 3-bit virtual IDs.
Module Instance
acpidmap
Offset:
0x5C
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
Altera Corporation
29 28 27 26
13 12 11 10
page Reserved
RO 0x0
Name
ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory
region.
This value is propagated to SCU as ARUSERS.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
page Reserved
RO 0x0
Bit Fields
25 24 23 22
Reserved
9 8 7 6
user
RO 0x0
Description
Base Address
0xFF707000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
user
RO 0x0
21 20 19 18
5 4 3 2
Reserved
Access
Register Address
0xFF70705C
21 20 19 18
5 4 3 2
Reserved
Cortex-A9 Microprocessor Unit Subsystem
cv_5v4
2016.10.28
17 16
1 0
Reset
RO 0x0
RO 0x0
17 16
1 0
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