Altera cyclone V Technical Reference page 9

Configuring the Flash Device.....................................................................................................15-10
XIP Mode...................................................................................................................................... 15-12
Write Protection........................................................................................................................... 15-12
Data Slave Sequential Access Detection................................................................................... 15-12
Clocks............................................................................................................................................ 15-12
Resets............................................................................................................................................. 15-13
Interrupts...................................................................................................................................... 15-13
Quad SPI Flash Controller Programming Model................................................................................15-14
Setting Up the Quad SPI Flash Controller................................................................................15-15
Indirect Read Operation with DMA Disabled.........................................................................15-15
Indirect Read Operation with DMA Enabled.......................................................................... 15-16
Indirect Write Operation with DMA Disabled........................................................................15-16
Indirect Write Operation with DMA Enabled......................................................................... 15-17
XIP Mode Operations................................................................................................................. 15-17
Quad SPI Flash Controller Address Map and Register Definitions..................................................15-19
QSPI Flash Controller Module Registers Address Map..........................................................15-20
QSPI Flash Module Data (AHB Slave) Address Map............................................................. 15-61
Document Revision History...................................................................................................................15-61
DMA Controller................................................................................................ 16-1
Features of the DMA Controller.............................................................................................................. 16-1
DMA Controller Block Diagram and System Integration....................................................................16-3
Functional Description of the DMA Controller.................................................................................... 16-3
AXI Characteristics for a DMA Transfer.................................................................................... 16-4
Operating States............................................................................................................................. 16-5
Initializing the DMAC...................................................................................................................16-8
Using the Slave Interfaces............................................................................................................. 16-9
Peripheral Request Interface.......................................................................................................16-10
Using Events and Interrupts....................................................................................................... 16-21
Aborts............................................................................................................................................ 16-23
Security Usage.............................................................................................................................. 16-26
Programming Restrictions..........................................................................................................16-29
Constraints and Limitations of Use...........................................................................................16-33
DMA Controller Programming Model.................................................................................................16-34
Instruction Syntax Conventions................................................................................................ 16-34
Instruction Set Summary............................................................................................................16-34
Instructions...................................................................................................................................16-35
Assembler Directives................................................................................................................... 16-50
MFIFO Buffer Usage Overview..................................................................................................16-52
DMA Controller Address Map and Register Definitions................................................................... 16-60
Address Map and Register Definitions..................................................................................... 16-62
Document Revision History...................................................................................................................16-63
Ethernet Media Access Controller.................................................................... 17-1
Features of the Ethernet MAC..................................................................................................................17-2
MAC.................................................................................................................................................17-2
DMA................................................................................................................................................ 17-2
TOC-9
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