Altera cyclone V Technical Reference page 217

cv_5v4
2016.10.28
Register
I2C3USEFPGA on page
5-234
I2C2USEFPGA on page
5-235
I2C1USEFPGA on page
5-235
SPIM1USEFPGA
5-236
SPIM0USEFPGA
5-237
siliconid1
Specifies Silicon ID and revision number.
Module Instance
sysmgr
Offset:
0x0
Access:
RO
31 30
15 14
siliconid1 Fields
Bit
31:16
id
System Manager
Send Feedback
Offset
0x724
0x728
0x72C
on page 0x730
on page 0x738
0xFFD08000
29 28 27 26
13 12 11 10
Name
Silicon ID
Value
0x0
Width Acces Reset Value
s
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
Base Address
Bit Fields
25 24 23 22
id
RO 0x0
9 8 7 6
rev
RO 0x1
Description
Description
HPS in Cyclone V and Arria V SoC FPGA
devices
siliconid1
Description
Select source for I2C3 signals
(HPS Pins or FPGA Interface)
Select source for I2C2 signals
(HPS Pins or FPGA Interface)
Select source for I2C1 signals
(HPS Pins or FPGA Interface)
Select source for SPIM1 signals
(HPS Pins or FPGA Interface)
Select source for SPIM0 signals
(HPS Pins or FPGA Interface)
Register Address
0xFFD08000
21 20 19 18
5 4 3 2
Access
RO
5-23
17 16
1 0
Reset
0x0
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