Altera cyclone V Technical Reference page 304

5-110
EMACIO4
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
EMACIO3 Fields
Bit
1:0
sel
EMACIO4
This register is used to control the peripherals connected to emac0_tx_d3 Only reset by a cold reset
(ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no
support for dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x410
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select peripheral signals connected emac0_tx_d2. 0 :
Pin is connected to GPIO/LoanIO number 3. 1 : Pin is
connected to Peripheral signal not applicable. 2 : Pin
is connected to Peripheral signal USB1.D2. 3 : Pin is
connected to Peripheral signal RGMII0.TXD2.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
0xFFD08000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
21 20 19 18
5 4 3 2
Access
Register Address
0xFFD08410
21 20 19 18
5 4 3 2
cv_5v4
2016.10.28
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
17 16
1 0
sel
RW 0x0
System Manager
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