Altera cyclone V Technical Reference page 894

Hard processor system
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cv_5v4
2016.10.28
31
30
15
14
spare_area_marker Fields
Bit
15:0
value
devices_connected
Number of Devices connected on one bank
Module Instance
nandregs
Offset:
0x250
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
15
14
NAND Flash Controller
Send Feedback
29
28
27
26
13
12
11
10
Name
The value that will be written in the spare area skip
bytes. This value will be used by controller while in
the MAIN mode of data transfer. Only the least-
significant 8 bits of the field value are used.
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
Reserved
Bit Fields
25
24
23
22
Reserved
9
8
7
6
value
RW 0xFFFF
Description
Base Address
Bit Fields
25
24
23
22
Reserved
9
8
7
6
devices_connected
21
20
19
18
5
4
3
2
Access
Register Address
0xFFB80250
21
20
19
18
5
4
3
2
13-73
17
16
1
0
Reset
RW
0xFFFF
17
16
1
0
value
RW 0x0
Altera Corporation

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