Altera cyclone V Technical Reference page 73

2-36
misc
Bit
24
outresetall
21:16
denom
15:3
numer
2
pwrdn
1
en
0
bgpwrdn
misc
Contains VCO control signals and other PLL control signals need to be controllable through register.
Fields are only reset by a cold reset.
Module Instance
clkmgr
Offset:
0x44
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
Name
Before releasing Bypass, All Output Counter Reset
must be set and cleared by software for correct clock
operation. If '1', Reset phase multiplexer and all
output counter state. So that after the assertion all the
clocks output are start from rising edge align. If '0',
phase multiplexer and output counter state not reset
and no change to the phase of the clock outputs.
Denominator in VCO output frequency equation. For
incremental frequency change, if the new value lead
to less than 20% of the frequency change, this value
can be changed without resetting the PLL. The
Numerator and Denominator can not be changed at
the same time for incremental frequency changed.
Numerator in VCO output frequency equation. Note
that the valid range for this field is 0x000 to 0xFFF (0
to 4095)​. The most significant bit of this field is
reserved and should not be used. For incremental
frequency change, if the new value lead to less than
20% of the frequency change, this value can be
changed without resetting the PLL. The Numerator
and Denominator can not be changed at the same
time for incremental frequency changed.
If '1', power down analog circuitry. If '0', analog
circuitry not powered down.
If '1', VCO is enabled. If '0', VCO is in reset.
If '1', powers down bandgap. If '0', bandgap is not
power down.
0xFFD04000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Base Address
0xFFD04044
2016.10.28
Access Reset
RW 0x0
RW 0x1
RW 0x1
RW 0x1
RW 0x0
RW 0x1
Register Address
Clock Manager
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