Altera cyclone V Technical Reference page 94

cv_5v4
2016.10.28
en Fields
Bit
11
qspiclk
10
nandclk
9
nandxclk
8
sdmmcclk
7
s2fuser1clk
6
gpioclk
5
can1clk
4
can0clk
3
spimclk
2
usbclk
1
emac1clk
0
emac0clk
div
Contains fields that control clock dividers for clocks derived from the Peripheral PLL Fields are only reset
by a cold reset.
Module Instance
clkmgr
Offset:
0xA4
Clock Manager
Send Feedback
Name
Enables clock qspi_clk output
Enables clock nand_clk output nand_clk Enable
should always be de-asserted before the nand_x_clk
Enable, and the nand_x_clk Enable should always be
asserted before the nand_clk Enable is asserted. A
brief delay is also required between switching the
enables (8 * nand_clk period).
Enables clock nand_x_clk output nand_clk Enable
should always be de-asserted before the nand_x_clk
Enable, and the nand_x_clk Enable should always be
asserted before the nand_clk Enable is asserted. A
brief delay is also required between switching the
enables (8 * nand_clk period).
Enables clock sdmmc_clk output
Enables clock s2f_user1_clk output. Qsys and user
documenation refer to s2f_user1_clk as h2f_user1_
clk.
Enables clock gpio_clk output
Enables clock can1_clk output
Enables clock can0_clk output
Enables clock spi_m_clk output
Enables clock usb_mp_clk output
Enables clock emac1_clk output
Enables clock emac0_clk output
0xFFD04000
Description
Base Address
0xFFD040A4
2-57
div
Access Reset
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
Register Address
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