Altera cyclone V Technical Reference page 524

7-76
USB1 Register Descriptions
31 30
15 14
fn_mod Fields
Bit
1
wr
0
rd
USB1 Register Descriptions
Registers associated with the USB1 master. This master is used to access the registers in USB1.
Offset:
0x8000
fn_mod_bm_iss
Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding
transactions.
ahb_cntl
on page 7-77
Sets the block issuing capability to one outstanding transaction.
fn_mod_bm_iss
Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding
transactions.
Module Instance
l3regs
Offset:
0xA008
Access:
RW
Altera Corporation
29 28 27 26
13 12 11 10
Name
Value
0x0
0x1
Value
0x0
0x1
on page 7-76
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Description
Multiple outstanding write transactions
Only a single outstanding write transaction
Description
Multiple outstanding read transactions
Only a single outstanding read transaction
Base Address
0xFF800000
21 20 19 18
5 4 3 2
Access
Register Address
0xFF80A008
System Interconnect
cv_5v4
2016.10.28
17 16
1 0
wr rd
RW RW 0x0
0x0
Reset
RW 0x0
RW 0x0
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