Altera cyclone V Technical Reference page 208

Hard processor system
Hide thumbs Also See for cyclone V:
Table of Contents

Advertisement

5-14
System Manager Module Address Map
Register
EMACIO3
on page 5-109
EMACIO4
on page 5-110
EMACIO5
on page 5-111
EMACIO6
on page 5-112
EMACIO7
on page 5-112
EMACIO8
on page 5-113
EMACIO9
on page 5-114
EMACIO10
on page 5-
115
EMACIO11
on page 5-
115
EMACIO12
on page 5-
116
EMACIO13
on page 5-
117
EMACIO14
EMACIO15
EMACIO16
EMACIO17
EMACIO18
EMACIO19
FLASHIO0
on page 5-
118
FLASHIO1
on page 5-
118
FLASHIO2
on page 5-
119
Altera Corporation
Offset
Width Acces
s
0x40C
32
RW
0x410
32
RW
0x414
32
RW
0x418
32
RW
0x41C
32
RW
0x420
32
RW
0x424
32
RW
0x428
32
RW
0x42C
32
RW
0x430
32
RW
0x434
32
RW
0x438
32
RW
0x43C
32
RW
0x440
32
RW
0x444
32
RW
0x448
32
RW
0x44C
32
RW
0x450
32
RW
0x454
32
RW
0x458
32
RW
Reset Value
emac0_tx_d2 Mux Selection
0x0
Register
emac0_tx_d3 Mux Selection
0x0
Register
emac0_rx_d0 Mux Selection
0x0
Register
emac0_mdio Mux Selection
0x0
Register
emac0_mdc Mux Selection
0x0
Register
emac0_rx_ctl Mux Selection
0x0
Register
emac0_tx_ctl Mux Selection
0x0
Register
emac0_rx_clk Mux Selection
0x0
Register
emac0_rx_d1 Mux Selection
0x0
Register
emac0_rx_d2 Mux Selection
0x0
Register
emac0_rx_d3 Mux Selection
0x0
Register
emac1_tx_clk Mux Selection
0x0
Register
emac1_tx_d0 Mux Selection
0x0
Register
emac1_tx_d1 Mux Selection
0x0
Register
emac1_tx_ctl Mux Selection
0x0
Register
emac1_rx_d0 Mux Selection
0x0
Register
emac1_rx_d1 Mux Selection
0x0
Register
sdmmc_cmd Mux Selection
0x0
Register
sdmmc_pwren Mux Selection
0x0
Register
sdmmc_d0 Mux Selection
0x0
Register
cv_5v4
2016.10.28
Description
System Manager
Send Feedback

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents