Altera cyclone V Technical Reference page 651

cv_5v4
2016.10.28
GIC Source Block
Interrupt
Number
58 CortexA9_1
59 CortexA9_1
60 CortexA9_1
61 CortexA9_1
62 CortexA9_1
63 CortexA9_1
64 SCU
65 SCU
66 SCU
67 L2-Cache
68 L2-Cache
69 L2-Cache
70 L2-Cache
71 DDR
72 FPGA
73 FPGA
74 FPGA
Cortex-A9 Microprocessor Unit Subsystem
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Interrupt Name
cpu1_deflags1
cpu1_deflags2
cpu1_deflags3
cpu1_deflags4
cpu1_deflags5
cpu1_deflags6
scu_parityfail0
scu_parityfail1
scu_ev_abort
l2_ecc_byte_wr_IRQ
l2_ecc_corrected_IRQ
l2_ecc_uncorrected_IRQ
l2_combined_IRQ
ddr_ecc_error_IRQ
FPGA_IRQ0
FPGA_IRQ1
FPGA_IRQ2
GIC Interrupt Map for the Cyclone V SoC HPS
Combined Interrupts
—
—
—
—
—
—
—
—
—
—
—
—
This interrupt combines:
, ,
DECERRINTR ECNTRINTR
, ,
ERRRDINTR ERRRTINTR
, ,
ERRWDINTR ERRWTINTR
, , and
PARRDINTR PARRTINTR
.
SLVERRINTR
—
—
—
—
9-15
Triggering
Level
Level
Level
Level
Level
Level
Edge
Edge
Edge
Edge
Edge
Edge
Level
Level
Level or
Edge
Level or
Edge
Level or
Edge
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