Programming Restrictions - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
- The DMAC uses the status of the corresponding
DMAWFP
for the peripheral to signal a request.
• If =0, then the peripheral is in the secure state. The DMAC:
PNS
• Executes an
• Sets the appropriate bit in the
• Sets the
• Moves the DMA channel to the Faulting completing state
• If =1, then the peripheral is in the non-secure state. The DMAC halts execution of the thread and
PNS
waits for the peripheral to signal a request.
and
DMALDP
control if it sends an acknowledgement to the peripheral.
• If =0, then the peripheral is in the secure state. The DMAC:
PNS
• Executes an
• Sets the appropriate bit in the
• Sets the
• Moves the DMA channel to the Faulting completing state
• If PNS =1, then the peripheral is in the non-secure state. The DMAC sends a message to the peripheral
to communicate when the data transfer is complete.
DMAFLUSHP
sends a flush request to the peripheral.
• If =0, then the peripheral is in the secure state. The DMAC:
PNS
• Executes an
• Sets the appropriate bit in the
• Sets the
• Moves the DMA channel to the Faulting completing state
• If =1, then the peripheral is in the non-secure state. The DMAC clears the state of the peripheral
PNS
and sends a message to the peripheral to resend its level status.
When a DMA channel thread is in the non-secure state, and a
program the channel to perform a secure AXI transaction, the DMAC:
1. Executes a
2. Sets the appropriate bit in the
3. Sets the
4. Moves the DMA channel thread to the Faulting completing state

Programming Restrictions

Certain restrictions apply when programming the DMAC.
DMA Controller
Send Feedback
NOP
bit in the
ch_periph_err
- The DMAC uses the status of the corresponding
DMASTP
NOP
bit in the
ch_periph_err
- The DMAC uses the status of the corresponding
NOP
bit in the
ch_periph_err
DMANOP
FSRC
bit in the
ch_rdwr_err FTRn
PNS
register corresponding to the DMA channel number
FSRC
register
FTRn
register corresponding to the DMA channel number
FSRC
register
FTRn
register corresponding to the DMA channel number
FSRC
register
FTRn
register corresponding to the DMA channel number
register
Programming Restrictions
bit in the register, to control if it waits
CR4
bit in the
PNS CR4
bit in the register, to control if it
PNS CR4
instruction attempts to
DMAMOV CCR
16-29
register, to
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