Altera cyclone V Technical Reference page 650

9-14
GIC Interrupt Map for the Cyclone V SoC HPS
GIC Source Block
Interrupt
Number
37 CortexA9_0
38 CortexA9_0
39 CortexA9_0
40 CortexA9_0
41 CortexA9_0
42 CortexA9_0
43 CortexA9_0
44 CortexA9_0
45 CortexA9_0
46 CortexA9_0
47 CortexA9_0
48 CortexA9_1
49 CortexA9_1
50 CortexA9_1
51 CortexA9_1
52 CortexA9_1
53 CortexA9_1
54 CortexA9_1
55 CortexA9_1
56 CortexA9_1
57 CortexA9_1
Altera Corporation
Interrupt Name
cpu0_parityfail_TLB
cpu0_parityfail_D_Outer
cpu0_parityfail_D_Tag
cpu0_parityfail_D_Data
cpu0_deflags0
cpu0_deflags1
cpu0_deflags2
cpu0_deflags3
cpu0_deflags4
cpu0_deflags5
cpu0_deflags6
cpu1_parityfail
cpu1_parityfail_BTAC
cpu1_parityfail_GHB
cpu1_parityfail_I_Tag
cpu1_parityfail_I_Data
cpu1_parityfail_TLB
cpu1_parityfail_D_Outer
cpu1_parityfail_D_Tag
cpu1_parityfail_D_Data
cpu1_deflags0
Combined Interrupts
—
—
—
—
—
—
—
—
—
—
—
This interrupt combines the
interrupts named:
cpu0_
.
parityfail_*
—
—
—
—
—
—
—
—
—
Cortex-A9 Microprocessor Unit Subsystem
cv_5v4
2016.10.28
Triggering
Edge
Edge
Edge
Edge
Level
Level
Level
Level
Level
Level
Level
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Level
Send Feedback