Altera cyclone V Technical Reference page 650

Hard processor system

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GIC Interrupt Map for the Cyclone V SoC HPS

Source Block

Altera Corporation

Interrupt Name

cpu0_parityfail_TLB

cpu0_parityfail_D_Outer

cpu0_parityfail_D_Tag

cpu0_parityfail_D_Data

cpu0_deflags0

cpu0_deflags1

cpu0_deflags2

cpu0_deflags3

cpu0_deflags4

cpu0_deflags5

cpu0_deflags6

cpu1_parityfail

cpu1_parityfail_BTAC

cpu1_parityfail_GHB

cpu1_parityfail_I_Tag

cpu1_parityfail_I_Data

cpu1_parityfail_TLB

cpu1_parityfail_D_Outer

cpu1_parityfail_D_Tag

cpu1_parityfail_D_Data

cpu1_deflags0

Combined Interrupts

This interrupt combines the

interrupts named:

parityfail_*

Cortex-A9 Microprocessor Unit Subsystem

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