Interrupts; Clock Usage By Module - Altera cyclone V Technical Reference

2-18

Interrupts

The hardware-managed clocks are forced to their safe mode values such that the following conditions
occur:
• The hardware-managed clocks are bypassed to
• Programmable dividers select the reset default values.
• The flash controller clocks multiplexer selects the output from the peripheral PLL.
• All clocks are enabled.
A write by software is the only way to clear the safe mode bit (
Note: Before coming out of safe mode, all registers and clocks must be configured correctly. It is possible
to program the clock manager in such a way that only a cold reset can return the clocks to a
functioning state. Altera strongly recommends using Altera-provided libraries to configure and
control HPS clocks.
Interrupts
The clock manager provides one interrupt output which is enabled using the interrupt enable register
( ). The interrupt is the OR of the bits in the interrupt status register (
intren
loss of lock for each of the three PLLs.

Clock Usage By Module

The following table lists every clock input generated by the clock manager to all modules in the HPS.
System clock names are global for the entire HPS and system clocks with the same name are phase-aligned
at all endpoints.
Table 2-12: Clock Usage By Module
Module Name
MPU subsystem
Altera Corporation
osc1_clk
System Clock Name
mpu_clk
mpu_periph_clk
dbg_at_clk
dbg_clk
mpu_l2_ram_clk
l4_mp_clk
, including counters in the main PLL.
) of the
safemode ctrl
) that indicate lock and
inter
Main clock for the MPU
subsystem
Peripherals inside the MPU
subsystem
Trace bus
Debug
L2 cache and Accelerator
Coherency Port (ACP) ID
mapper
ACP ID mapper control slave
cv_5v4
2016.10.28
register.
Use
Clock Manager
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