Altera cyclone V Technical Reference page 323

cv_5v4
2016.10.28
GENERALIO2 Fields
Bit
1:0
sel
GENERALIO3
This register is used to control the peripherals connected to trace_d2 Only reset by a cold reset (ignores
warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for
dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x48C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
GENERALIO3 Fields
Bit
1:0
sel
System Manager
Send Feedback
Name
Select peripheral signals connected trace_d1. 0 : Pin is
connected to GPIO/LoanIO number 50. 1 : Pin is
connected to Peripheral signal UART0.TX. 2 : Pin is
connected to Peripheral signal SPIS0.MOSI. 3 : Pin is
connected to Peripheral signal TRACE.D1.
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select peripheral signals connected trace_d2. 0 : Pin is
connected to GPIO/LoanIO number 51. 1 : Pin is
connected to Peripheral signal I2C1.SDA. 2 : Pin is
connected to Peripheral signal SPIS0.MISO. 3 : Pin is
connected to Peripheral signal TRACE.D2.
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
GENERALIO3
Access
Register Address
0xFFD0848C
21 20 19 18
5 4 3 2
Access
5-129
Reset
RW 0x0
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
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