Clock Manager Block Diagram And System Integration - Altera cyclone V Technical Reference

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Clock Manager Block Diagram and System Integration

• Allows software to observe the status of all writable registers
• Supports interrupting the MPU subsystem on PLL-lock and loss-of-lock
• Supports clock gating at the signal level
The clock manager is not responsible for the following functional behaviors:
• Selection or management of the clocks for the FPGA-to-HPS and HPS-to-FPGA interfaces. The FPGA
logic designer is responsible for selecting and managing these clocks.
• Software must not program the clock manager with illegal values. If it does, the behavior of the clock
manager is undefined and could stop the operation of the HPS. The only guaranteed means for
recovery from an illegal clock setting is a cold reset.
• When re-programming clock settings, there are no automatic glitch-free clock transitions. Software
must follow a specific sequence to ensure glitch-free clock transitions. Refer to Hardware-Managed and
Software-Managed Clocks section of this chapter.
Related Information
Hardware-Managed and Software-Managed Clocks
•
Hardware-Managed and Software-Managed Clocks
•
Clock Manager Block Diagram and System Integration
Figure 2-1: Clock Manager Block Diagram
The following figure shows the major components of the clock manager and its integration in the HPS.
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2016.10.28
Clock Manager
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