Altera cyclone V Technical Reference page 813

cv_5v4
2016.10.28
31 30
15 14
mpweight_0_4 Fields
Bit
31:0
staticweight_31_0
mpweight_1_4
This register is used to configure the DRAM burst operation scheduling.
Module Instance
sdr
Offset:
0x50B4
Access:
RW
31 30
15 14
SDRAM Controller Subsystem
Send Feedback
29 28 27 26
13 12 11 10
Name
Set static weight of the port. Each port is programmed
with a 5 bit value. Port 0 is bits 4:0, port 1 is bits 9:5,
up to port 9 being bits 49:45
0xFFC20000
29 28 27 26
sumofweights_13_0
13 12 11 10
Bit Fields
25 24 23 22
staticweight_31_0
RW 0x0
9 8 7 6
staticweight_31_0
RW 0x0
Description
Base Address
Bit Fields
25 24 23 22
RW 0x0
9 8 7 6
staticweight_49_32
RW 0x0
mpweight_1_4
21 20 19 18
5 4 3 2
Access
Register Address
0xFFC250B4
21 20 19 18
5 4 3 2
11-75
17 16
1 0
Reset
RW 0x0
17 16
staticweight_
49_32
RW 0x0
1 0
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