Emac Block Diagram And System Integration - Altera cyclone V Technical Reference

17-4

EMAC Block Diagram and System Integration

EMAC Block Diagram and System Integration
Figure 17-1: EMAC System Integration
PHY
PHY
RGMII_0
PHY_0
MDIO_0/I2C_2
RGMII_1
PHY_1
MDIO_1/I2C_3
The EMACs are integrated into the HPS portion of the system on a chip (SoC) device. They communicate
with the I/O pins.
EMAC Overview
Each EMAC is an internal bus master that sends Ethernet packets to and from the System Interconnect.
The EMAC uses a descriptor ring protocol, where the descriptor contains an address to a buffer to fetch or
store the packet data.
Each EMAC has an MDIO Management port to send commands to the external PHY. Alternatively, you
can use an I
Each EMAC has an IEEE 1588 Timestamp interface with 20 ns resolution. The ARM Cortex-A9
microprocessor unit (MPU) subsystem can use it to maintain synchronization between the time counters
that are internal to the three MACs. The clock reference for the timestamp can be provided by the Clock
Altera Corporation
Optional
Adaptor Logic
Pin
Multiplexer
TMSTP= Timestamp
2
C module in the HPS for the management interface.
TMSTP
PHY DMA
EMAC0
MDIO CSR
TMSTP
PHY DMA
EMAC1
MDIO CSR
I2C_2 (for Ethernet)
I2C_3 (for Ethernet)
FPGA
1588
Control
AXI
APB
Interconnect
AXI
APB
HPS
Ethernet Media Access Controller
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cv_5v4
2016.10.28
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