Altera cyclone V Technical Reference page 109

2-72
stat
en Fields
Bit
3
s2fuser2clk
2
ddrdqclk
1
ddr2xdqsclk
0
ddrdqsclk
stat
Contains Output Clock Counter Reset acknowledge status.
Module Instance
clkmgr
Offset:
0xDC
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
Name
Enables clock s2f_user2_clk output. Qsys and user
documenation refer to s2f_user2_clk as h2f_user2_
clk.
Enables clock ddr_dq_clk output
Enables clock ddr_2x_dqs_clk output
Enables clock ddr_dqs_clk output
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Description
Base Address
0xFFD04000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Access
Register Address
0xFFD040DC
21 20 19 18
5 4 3 2
outresetack
RO 0x0
cv_5v4
2016.10.28
Reset
RW 0x1
RW 0x1
RW 0x1
RW 0x1
17 16
1 0
Clock Manager
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