Cyclic Dependency Avoidance Schemes - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

Cyclic Dependency Avoidance Schemes

The AXI protocol permits re-ordering of transactions. As a result, when routing concurrent multiple
transactions from a single point of divergence to multiple slaves, the interconnect might need to enforce
rules to prevent deadlock.
Each master of the interconnect is configured with one of three possible cyclic dependency avoidance
schemes (CDAS). The same CDAS scheme is configured for both read and write transactions, but they
operate independently.
Single Slave
Single Slave Per ID
Single Active Slave
Related Information
System Interconnect Master Properties
Contains descriptions of the CDAS implementation for the masters.
Single Slave
Single slave (SS) ensures the following conditions at a slave interface of a switch:
• All outstanding read transactions are to a single end destination.
• All outstanding write transactions are to a single end destination.
If a master issues another transaction to a different destination than the current destination for that
transaction type (read or write), the network stalls the transactions until all the outstanding transactions of
that type have completed.
Single Slave Per ID
Single slave per ID (SSPID) ensures the following conditions at a slave interface of a switch:
• All outstanding read transactions with the same ID go the same destination.
• All outstanding write transactions with the same ID go the same destination.
When a master issues a transaction, the following situations can occur:
• If the transaction has an ID that does not match any outstanding transactions, it passes the CDAS.
• If the transaction has an ID that matches the ID of an outstanding transaction, and the destinations
also match, it passes the CDAS.
• If the transaction has an ID that matches the ID of an outstanding transaction, and the destinations do
not match, the transaction fails the CDAS check and stalls.
Single Active Slave
Single active slave (SAS) is the same as the SSPID scheme, with an added check for write transactions. SAS
ensures that a master cannot issue a new write address until all of the data from the previous write transac‐
tion has been sent.
System Interconnect
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Cyclic Dependency Avoidance Schemes
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