Cpu Prefetch - Altera cyclone V Technical Reference

9-68
Cache Latency
Memory Management Unit
•
Information about how the address space is set based on L2 cache address filtering.
Cache Latency
Latency for cache hits and misses varies.
The latency for an L1 cache hit is 1 clock. The latency for an L1 cache miss and L2 cache hit is 6 clocks best
case. Latency in the L2 cache can vary depending on other operations in the L2. Parity and ECC settings
have no effect on latency. A single-bit ECC error is corrected during the L2 read, but is not re-written to
the L2 RAM.

CPU Prefetch

The Cortex-A9 performs instruction and data prefetches regardless of the state of the MMU.
A prefetch occurs when any address that is 4 KB above the current instruction pointer is accessed. The
system has been designed to ensure that the system bus does not lock on prefetches. Any prefetches to
unmapped memory space produce a decode error on the system interconnect.
Debugging Modules
The MPU subsystem includes debugging resources through ARM CoreSight on-chip debugging and trace.
The following functionality is included:
• Individual program trace for each processor
• Event trace for the Cortex-A9 MPCore
• Cross triggering between processors and other HPS debugging features
Program Trace
Each processor has an independent program trace monitor (PTM) that provides real-time instruction flow
trace. The PTM is compatible with a number of third-party debugging tools.
The PTM provides trace data in a highly compressed format. The trace data includes tags for specific
points in the program execution flow, called waypoints. Waypoints are specific events or changes in the
program flow.
The PTM recognizes and tags the waypoints listed in
Table 9-13: Waypoints Supported by the PTM
Indirect branches
Direct branches
Instruction barrier instructions
Exceptions
Altera Corporation
on page 9-9
Type
Table 9-13.
Additional Waypoint Information
Target address and condition code
Condition code
—
Location where the exception occurred
Cortex-A9 Microprocessor Unit Subsystem
cv_5v4
2016.10.28
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