Features Of Coresight Debug And Trace - Altera cyclone V Technical Reference

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Features of CoreSight Debug and Trace

Features of CoreSight Debug and Trace
The CoreSight debug and trace system offers the following features:
• Real-time program flow instruction trace through a separate Program Trace Macrocell (PTM) for each
processor
• Host debugger JTAG interface
• Connections for cross-trigger and STM-to-FPGA interfaces, which enable soft IP generation of triggers
and system trace messages
• External trace interface through Trace Port Interface Unit (TPIU) for trace analysis tools
• Custom message injection through the System Trace Macrocell (STM) into the trace stream for delivery
to a host debugger
• STM and PTM trace sources multiplexed into a single stream through the Trace Funnel
• Capability to route trace data to any slave accessible to the Embedded Trace Router (ETR) AXI master
connected to the level 3 (L3) interconnect
• Capability for the following components to trigger each other through the embedded cross-trigger
system:
• Cortex-A9 PTM-0
• Cortex-A9 PTM-1
• STM
• Embedded Trace FIFO (ETF)
• ETR
• TPIU
• csCross Trigger Interface (CTI)
• FPGA-CTI
• csCross Trigger Matrix (CTM)
Related Information
Cross Trigger Interface
ARM CoreSight Documentation
The following ARM CoreSight specifications and documentation provide a more thorough description of
the ARM CoreSight components in the HPS debug system:
• CoreSight Technology System Design Guide (ARM DGI 0012D)
• CoreSight Architecture Specification
• Embedded Cross Trigger Technical Reference Manual (ARM DDI 0291A)
• CoreSight Components Technical Reference Manual (ARM DDI 0314H)
• CoreSight System Trace Macrocell Technical Reference Manual (ARM DDI 0444A)
• System Trace Macrocell Programmers' Model Architecture Specification (ARM IHI 0054)
• CoreSight Trace Memory Controller Technical Reference Manual (ARM DDI 0461B)
Altera Corporation
on page 10-8
cv_5v4
2016.10.28
CoreSight Debug and Trace
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