Arm Jtag-Ap Scan Chains - Altera cyclone V Technical Reference

Hard processor system
Hide thumbs Also See for cyclone V:
Table of Contents

Advertisement

cv_5v4
2016.10.28
Signal
SRSTCONNECTED[7:0]
PORTCONNECTED[7:0]
PORTENABLED[7:0]
nSRSTOUT[7:0]
nTRST*[7:0]
Related Information
stat
on page 6-9
Information about configuring the scan manager's stat register
Communicating with the JTAG TAP Controller
http://infocenter.arm.com
For detailed information about the ARM JTAG-AP
Components chapter of the CoreSight SoC Technical Reference Manual , which you can download from
the ARM Infocenter website.

ARM JTAG-AP Scan Chains

The ARM JTAG-AP supports up to eight scan chains. The scan manager uses only scan chains 0, 1, 2, 3,
and 7.
Scan chain 7 of the JTAG-AP connects to FPGA JTAG TAP controller. When the system manager
undergoes a cold reset, this connection is disabled and the FPGA JTAG pins are connected to the FPGA
JTAG TAP controller. You can configure the system manager to enable the connection, which allows
software running on the HPS to communicate with the FPGA JTAG TAP controller. In this case, software
Scan Manager
Send Feedback
Direction
Input
Tied to 0. The read-only
register always reads as 0.
CSW
Input
Tied to 0x8F, which connects only ports 0-3 and 7.
The read-only
register reads as 1 when the
written with a value that enables one of the
connected ports, and reads as 0 otherwise.
Input
Tied to 0x8F, so all connected ports are always
considered powered on. The ARM JTAG AP
register is not supported. Software does not need to
monitor the status of ports 0-3 because they are
always on. For port 7, software can read the
field of the
determine the FPGA power status.
Output
Not connected. Writing to the
register has no effect.
CSW
Output
nTRST*[7]
controller and
Writing to the
(the
trst
manager) has an effect only when port 7 is enabled
by software. For details, refer to "Communicating
with the JTAG TAP Controller".
on page 6-6
CSW
ARM JTAG-AP Scan Chains
Implementation
SRSTCONNECTED
field in the
PORTCONNECTED
PORTSEL
register in the FPGA manager to
stat
SRST_OUT
is connected to the FPGA JTAG TAP
are not connected.
nTRST*[6:0]
field of the
TRST_OUT
bit of the
register in the scan
stat
,
, and
registers, refer to the DAP
PORTSEL
PSTA
6-3
field in the
CSW
register is
PSTA
mode
field of the
register
CSW
Altera Corporation

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents