Altera cyclone V Technical Reference page 7

SDRAM Controller Subsystem Programming Model........................................................................ 11-32
HPS Memory Interface Architecture.........................................................................................11-32
HPS Memory Interface Configuration......................................................................................11-32
HPS Memory Interface Simulation........................................................................................... 11-33
Generating a Preloader Image for HPS with EMIF.................................................................11-33
Debugging HPS SDRAM in the Preloader........................................................................................... 11-35
Enabling UART or Semihosting Printout.................................................................................11-35
Enabling Simple Memory Test................................................................................................... 11-36
Enabling the Debug Report........................................................................................................ 11-37
Writing a Predefined Data Pattern to SDRAM in the Preloader...........................................11-40
SDRAM Controller Address Map and Register Definitions.............................................................. 11-41
SDRAM Controller Address Map..............................................................................................11-41
Document Revision History...................................................................................................................11-77
On-Chip Memory.............................................................................................. 12-1
On-Chip RAM............................................................................................................................................12-1
Features of the On-Chip RAM..................................................................................................... 12-1
On-Chip RAM Block Diagram and System Integration...........................................................12-1
Functional Description of the On-Chip RAM........................................................................... 12-2
Boot ROM................................................................................................................................................... 12-3
Features of the Boot ROM............................................................................................................ 12-3
Boot ROM Block Diagram and System Integration..................................................................12-3
Functional Description of the Boot ROM.................................................................................. 12-3
On-Chip Memory Address Map and Register Definitions.................................................................. 12-4
On-chip RAM Address Map.........................................................................................................12-4
Boot ROM Address Map...............................................................................................................12-4
Document Revision History.....................................................................................................................12-4
NAND Flash Controller.................................................................................... 13-1
NAND Flash Controller Features............................................................................................................ 13-1
NAND Flash Controller Block Diagram and System Integration.......................................................13-2
NAND Flash Controller Signal Descriptions......................................................................................... 13-2
Functional Description of the NAND Flash Controller....................................................................... 13-3
Discovery and Initialization......................................................................................................... 13-3
Bootstrap Interface.........................................................................................................................13-4
Configuration by Host...................................................................................................................13-5
Local Memory Buffer.....................................................................................................................13-6
Clocks.............................................................................................................................................. 13-6
Resets............................................................................................................................................... 13-7
Indexed Addressing....................................................................................................................... 13-7
Command Mapping...................................................................................................................... 13-8
Data DMA.....................................................................................................................................13-14
ECC................................................................................................................................................13-18
NAND Flash Controller Programming Model....................................................................................13-21
Basic Flash Programming........................................................................................................... 13-22
Flash-Related Special Function Operations............................................................................. 13-25
NAND Flash Controller Address Map and Register Definitions...................................................... 13-33
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