Altera cyclone V Technical Reference page 810

11-72
mppriority
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
protrulerdwr Fields
Bit
6
readrule
5
writerule
4:0
ruleoffset
mppriority
This register is used to configure the DRAM burst operation scheduling.
Module Instance
sdr
Offset:
0x50AC
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
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software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Write to this bit to have the memory_prot_data
register loaded with the value from the internal
protection table at offset. Table value will be loaded
before a rdy is returned so read data from the register
will be correct for any follow-on reads to the
memory_prot_data register.
Write to this bit to have the memory_prot_data
register to the table at the offset specified by port_
offset. Bit automatically clears after a single cycle and
the write operation is complete.
This field defines which of the 20 rules in the
protection table you want to read or write.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
Reserved
9 8 7 6
readr
ule
RW
0x0
Description
Base Address
0xFFC20000
21 20 19 18
5 4 3 2
write ruleoffset
rule
RW 0x0
RW
0x0
Register Address
0xFFC250AC
SDRAM Controller Subsystem
cv_5v4
2016.10.28
17 16
1 0
Access Reset
RW 0x0
RW 0x0
RW 0x0
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