Altera cyclone V Technical Reference page 954

14-8
Interrupt Controller Unit
Interrupt Controller Unit
The interrupt controller unit generates an interrupt that depends on the
mask register (
interrupt condition is detected, the controller sets the corresponding interrupt bit in the
The bit in the
bit; writing a 0 leaves the bit untouched.
The interrupt controller unit generates active high, level sensitive interrupts that are asserted only when at
least one bit in the
int_enable
The
int_enable
are set to 0x0000000, which masks all the interrupts.
Table 14-4: Interrupt Status Register Bits
Bits
16 SDIO Interrupts
15 End Bit Error (read)/Write no CRC (EBE)
14 Auto Command Done (ACD)
13 Start Bit Error (SBE)
12 Hardware Locked write Error (HLE)
Altera Corporation
), and the interrupt enable bit (
intmask
register remains set until the software clears the bit by writing a 1 to the interrupt
rintsts
register is set to 1, the corresponding
rintsts
bit of the register is 1.
ctrl
bit of the register is cleared during a power-on reset, and the
ctrl
†
Interrupt
†
†
int_enable
Interrupts from SDIO cards.
†
Error in end-bit during read operation, or no
data CRC received during write operation.
Note: For MMC CMD19, there may be no
CRC status returned by the card.
Hence, EBE is set for CMD19. The
application should not treat this as an
error.
Stop/abort commands automatically sent by
card unit and not initiated by host; similar to
Command Done (CD) interrupt.
Recommendation: Software typically need not
enable this for non CE-ATA accesses; Data
Transfer Over (DTO) interrupt that comes after
this interrupt determines whether data transfer
has correctly competed. For CE-ATA accesses, if
the software sets
the control register, then software should enable
†
this bit.
Error in data start bit when data is read from a
card. In 4-bit mode, if all data bits do not have
start bit, then this error is set.
†
During hardware-lock period, write attempted
to one of locked registers.
register, the interrupt
rintsts
) of the control register (
rintsts
register bit is 1, and the
intmask
intmask
Description
†
†
†
send_auto_stop_ccsd
†
SD/MMC Controller
cv_5v4
2016.10.28
). Once an
ctrl
register.
register bits
†
bit in
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