Altera cyclone V Technical Reference page 279

cv_5v4
2016.10.28
Bit
3
serr
2
injd
1
injs
0
en
nand
This register is used to enable ECC on the NAND RAM. ECC errors can be injected into the write path
using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only
reset by a cold reset (ignores warm reset).
Module Instance
sysmgr
Offset:
0x164
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
System Manager
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Name
This bit is an interrupt status bit for CAN1 RAM ECC
single, correctable error. It is set by hardware when
single, correctable error occurs in CAN1 RAM.
Software needs to write 1 into this bit to clear the
interrupt status.
Changing this bit from zero to one injects a double,
non-correctable error into the CAN1 RAM. This only
injects one double bit error into the CAN1 RAM.
Changing this bit from zero to one injects a single,
correctable error into the CAN1 RAM. This only
injects one error into the CAN1 RAM.
Enable ECC for CAN1 RAM
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
rdfif rdfif wrfif
oderr oserr oderr
RW RW RW
0x0 0x0 0x0
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
wrfif eccbu eccbu rdfif
oserr fderr fserr oinjd
RW RW RW RW
0x0 0x0 0x0 0x0
Access
Register Address
0xFFD08164
21 20 19 18
5 4 3 2
rdfif wrfif wrfif eccbu
oinjs oinjd oinjs finjd
RW RW RW RW
0x0 0x0 0x0 0x0
5-85
nand
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
17 16
1 0
eccbu en
finjs
RW 0x0
RW
0x0
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