Altera cyclone V Technical Reference page 921

13-100
intr_en1
Bit
5
erase_fail
4
program_fail
3
time_out
2
dma_cmd_comp
1
RSVD
0
ecc_uncor_err
intr_en1
Enables corresponding interrupt bit in interrupt register for bank 1
Module Instance
nandregs
Offset:
0x470
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
page_ pipe_ rst_
xfer_inc cmd_ comp
err
RW 0x0
RW
0x0
Altera Corporation
Name
Erase failure occurred in the device on issuance of a
erase command. err_block_addr and err_page_addr
contain the block address and page address that failed
erase operation.
Program failure occurred in the device on issuance of
a program command. err_block_addr and err_page_
addr contain the block address and page address that
failed program operation.
Watchdog timer has triggered in the controller due to
one of the reasons like device not responding or
controller state machine did not get back to idle
A data DMA command has completed on this bank.
RSVD
Ecc logic detected uncorrectable error while reading
data from flash device.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
INT_ unsup locke
act _cmd d_blk
RW RW RW RW
0x1 0x0 0x0 0x0
Description
Base Address
0xFFB80000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
pipe_ erase progr load_
cpybc _comp am_ comp
k_ comp
RW RW
cmd_
0x0 RW 0x0
comp
0x0
RW
0x0
Register Address
0xFFB80470
21 20 19 18
5 4 3 2
erase progr time_ dma_
_fail am_ out cmd_
fail comp
RW RW
0x0 RW 0x0 RW
0x0 0x0
NAND Flash Controller
cv_5v4
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
R 0x0
RW 0x0
17 16
1 0
Reser ecc_
ved uncor_
err
RW 0x0
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