Ce-Ata Data Transfer Commands - Altera cyclone V Technical Reference

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Read-Wait Sequence
Single-Block or Multiple-Block Read
•
Refer to this section for more information about writing to the
Single-Block or Multiple-Block Write
•
Refer to this section for more information about writing to the
Read-Wait Sequence
Read_wait is used with SDIO cards only. It temporarily stalls the data transfer, either from functions or
memory, and allows the host to send commands to any function within the SDIO card device. The host
can stall this transfer for as long as required. The controller provides the facility to signal this stall transfer
to the card.
Signalling a Stall
To signal the stall, perform the following steps:
1. Check if the card supports the read_wait facility by reading the SDIO card's SRW bit, bit 2 at offset 0x8
in the CCCR.
2. If this bit is 1, all functions in the card support the read_wait facility. Use the SD/SDIO
IO_RW_DIRECT command to read this bit.
3. If the card supports the
register to 1.
4. Reset the

CE-ATA Data Transfer Commands

This section describes CE-ATA data transfer commands.
Related Information
Data Transfer Commands
Refer to this section for information about the basic settings and interrupts generated for different
conditions.
ATA Task File Transfer Overview
ATA task file registers are mapped to addresses 0x00h through 0x10h in the MMC register space. The
RW_REG command is used to issue the ATA command, and the ATA task file is transmitted in a single
RW_REG MMC command sequence.
The host software stack must write the task file image to the FIFO buffer before setting the
registers in the controller. The host processor then writes the address and byte count to the
before setting the
For the RW_REG command, there is no CCS from the CE-ATA card device.
ATA Task File Transfer Using the RW_MULTIPLE_REGISTER (RW_REG) Command
This command involves data transfer between the CE-ATA card device and the controller. To send a data
command, the controller needs a command argument, total data size, and block size. Software receives or
sends data through the FIFO buffer.
Implementing ATA Task File Transfer
To implement an ATA task file transfer (read or write), perform the following steps:
Altera Corporation
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†
read_wait
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bit to 0 in the
read_wait
on page 14-49
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register bits.
cmd
on page 14-50
on page 14-53
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signal, assert it by setting the read wait bit (
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register.
ctrl
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register.
cmd
register.
cmd
read_wait
cmdarg
†
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SD/MMC Controller
cv_5v4
2016.10.28
) in the
ctrl
and
cmd
register
cmdarg
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