Altera cyclone V Technical Reference page 611

Hard processor system
Hide thumbs Also See for cyclone V:
Table of Contents

Advertisement

cv_5v4
2016.10.28
fn_mod2 Fields
Bit
0
bypass_merge
fn_mod
Sets the block issuing capability to multiple or single outstanding transactions.
Module Instance
hps2fpgaregs
Offset:
0x2108
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
15
14
fn_mod Fields
Bit
1
wr
HPS-FPGA Bridges
Send Feedback
Name
Controls bypass merge of upsizing/downsizing.
Value
0x0
0x1
0xFF500000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
Name
Value
0x0
0x1
Description
Description
The network can alter transactions.
The network does not alter any transactions
that could pass through the upsizer legally
without alteration.
Base Address
Bit Fields
25
24
23
22
Reserved
9
8
7
6
Reserved
Description
Description
Multiple outstanding write transactions
Only a single outstanding write transaction
fn_mod
Access
Register Address
0xFF502108
21
20
19
18
5
4
3
2
Access
8-29
Reset
RW
0x0
17
16
1
0
wr
rd
RW
RW 0x0
0x0
Reset
RW
0x0
Altera Corporation

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents