Altera cyclone V Technical Reference page 189

4-46
gpio_ver_id_code
31 30
15 14
gpio_ls_sync Fields
Bit
0
gpio_ls_sync
gpio_ver_id_code
GPIO Component Version
Module Instance
fpgamgrregs
Offset:
0x86C
Access:
RO
31 30
15 14
Altera Corporation
29 28 27 26
13 12 11 10
Name
The level-sensitive interrupts is synchronized to l4_
mp_clk.
Value
0x0
0x1
29 28 27 26
13 12 11 10
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Description
No synchronization to l4_mp_clk
Synchronize to l4_mp_clk
Base Address
0xFF706000
Bit Fields
25 24 23 22
gpio_ver_id_code
RO 0x3230382A
9 8 7 6
gpio_ver_id_code
RO 0x3230382A
21 20 19 18
5 4 3 2
Access
Register Address
0xFF70686C
21 20 19 18
5 4 3 2
cv_5v4
2016.10.28
17 16
1 0
gpio_ls_
sync
RW 0x0
Reset
RW 0x0
17 16
1 0
FPGA Manager
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